51802 debug mode consuming less power?

[Borden]

Hi community, I'm running a 51802 on my custom board with no other parts on it, except for some buttons and leds directly connected to GPIO, and a DC/DC converter which feed the 51802 with 1.8V power directly. I'm running a custom 2.4G protocol with neither softdevices, nor Gazell lib, which keep 16M clock always running.

Now when I try to optimize power, I've found some interesting thing that I can't find an explanation. I measure current before the DC/DC, so the absolute current read is not so relevant. The cpu is running the main loop steadily merely check for GPIO buttons, not much radio activities except sending a heartbeat packet every second,

the current read 2.21mA.

But if I reset the board to debug mode(with jlink plugged),

the current read 0.96mA.

I've checked this many times to make sure, as long as power is on, the consumption keeps the low state, and there seems no difference of the functionality of the 51802.

So my question is: why in debug mode, the power consumption reduced to about 44% of the normal state? what's changed inside the chip?

[Sigurd]

Hi,

It’s actually the other way around. When you do a power-reset, the nRF51 will exit debug mode. Debug mode consumes around ~1mA, so you will see a ~1mA reduction when you resume normal mode. Please see section 11.1.3 "Resuming Normal Mode" in the nRF51 reference manual

[Borden]

Yes I've had the same thought, so I've experimented, it's not leakage. Once the chip is in debug mode, it stays at 0.96mA, even after I pull the jlink off, until another power cycle.

And for the gpio polling, thanks for your advice, I know it's not efficient, but I'd like to optimize that after this problem made clear, step by step. The main reason that I haven't use the GPIOTE is it can't detect both edge at the same time, and my number of buttons is more than 4, make the GPIOTE inapplicable in my case, not even the extra power it needs, since my 16M clock is always running, I don't think it will draw more power.