51802 debug mode consuming less power?

[Borden]

Hi community, I'm running a 51802 on my custom board with no other parts on it, except for some buttons and leds directly connected to GPIO, and a DC/DC converter which feed the 51802 with 1.8V power directly. I'm running a custom 2.4G protocol with neither softdevices, nor Gazell lib, which keep 16M clock always running.

Now when I try to optimize power, I've found some interesting thing that I can't find an explanation. I measure current before the DC/DC, so the absolute current read is not so relevant. The cpu is running the main loop steadily merely check for GPIO buttons, not much radio activities except sending a heartbeat packet every second,

the current read 2.21mA.

But if I reset the board to debug mode(with jlink plugged),

the current read 0.96mA.

I've checked this many times to make sure, as long as power is on, the consumption keeps the low state, and there seems no difference of the functionality of the 51802.

So my question is: why in debug mode, the power consumption reduced to about 44% of the normal state? what's changed inside the chip?

[Sigurd]

Hi,

It’s actually the other way around. When you do a power-reset, the nRF51 will exit debug mode. Debug mode consumes around ~1mA, so you will see a ~1mA reduction when you resume normal mode. Please see section 11.1.3 "Resuming Normal Mode" in the nRF51 reference manual

[Borden]

I've already had a pull down resistor on SWDCLK pin. It's unlikely that my board entered debug mode at the first place. As you can see, after I triggered my board into debug mode using jlink, I long pushed a button on the back of the board to turn it off, then we read a 2.32mA in system off mode, that can prove the board is in debug mode. Then I pushed the button again to turn the board on, it's still 0.88mA, I believe that's the power consumption of the debug mode.