51802 debug mode consuming less power?

[Borden]

Hi community, I'm running a 51802 on my custom board with no other parts on it, except for some buttons and leds directly connected to GPIO, and a DC/DC converter which feed the 51802 with 1.8V power directly. I'm running a custom 2.4G protocol with neither softdevices, nor Gazell lib, which keep 16M clock always running.

Now when I try to optimize power, I've found some interesting thing that I can't find an explanation. I measure current before the DC/DC, so the absolute current read is not so relevant. The cpu is running the main loop steadily merely check for GPIO buttons, not much radio activities except sending a heartbeat packet every second,

the current read 2.21mA.

But if I reset the board to debug mode(with jlink plugged),

the current read 0.96mA.

I've checked this many times to make sure, as long as power is on, the consumption keeps the low state, and there seems no difference of the functionality of the 51802.

So my question is: why in debug mode, the power consumption reduced to about 44% of the normal state? what's changed inside the chip?

[Borden]

nrf51422_xxac.hex

Hi Sigurd, here's the hex file for you to test, it works with S130v2.0.1, thanks!

[Sigurd]

Hi Borden,

I have now tested on a 51802, but it act the same as the 51822. The 51802 uses abit more current overall than the 51822, but the 51802 also uses more current in debug mode than in normal mode for me. Actaully for me it uses 1.6 mA more in debug mode.

Are you sure that the chip is actually working when you have it debug mode? is the debug mode interfering with any other components on your board? Are you using a original/legal(non-copy) debugger?

You could also ask for a design review in mypage. Remember to upload all schematics and geber files.