circuit design for line debugging

[mdever]

I'm employing 51822AA.

I need to debug firmware for this chip line by line. Like environment of ARM9 with Lauterbach TRACE32 through JTAG.

Is line debugging possible with Segger's JTAG Base through just 4 pins(GND, VRF, DIO, CLK)?

Or any reference circuit design capable of line debugging with any in-circuit-debugger?

I can't see any change of data in real time.

[endnode]

nRF51 is using SWD not full JTAG so you need to connect SWDCLK and SWDIO wires (+ GND of course and you need to power whole system so typically 3V3 VDD is connected as 4th wire. Read more about it in chapter 11 of Reference Manual. Then you can perform halt/step "line by line" debugging in case you have some SWD capable HW and SW which understand ARM Cortex-M0 architecture (not sure if it needs to know some more specifics of nRF51 or if that is enough).

Note that if you use non-monolytic app e.g. with some radio stack (like Nordic Soft Device) then indeed your debugger will interfere with RTOS running in that stack and will be breaking the functionality. But if your FW is the only app which works with the highest interrupt priority then you can do it (still if you run some time-critical application it will be breaking by your halts;)

Good luck

[mdever]

I believe circuit design is no problem cause I can download binary. But while I debug with KEIL, it shows its debugging info for the first 2~3 steps but not for a few steps. What's wrong?

• Chip : nRF51822AA

  • Compiler : MDK-Lite 5.20

  • In Circuit Debugger : J-link base