UARTE FLUSHRX&RXFIFO

[Stayhungry]

Thanks for reading my question.

I use SDK14 , PCA10040, S132 and modified a little bit of uarte driver, but that should not affect what I said below.

I set the DMA buffer to 10 bytes, did not use the double buffer, and then sent to the UARTE 3 bytes, 10ms timer interrupt generated when the trigger TASK_STOPRX.

Followed by the END RX interrupt, I read the amount = 3, RXTO interrupt, I also read the amount = 3, and then in the RXTO interrupt, the PTR will be given a new buffer, MAXCNT = 10, and then trigger TASK_FLUSHRX, Followed by the END RX interrupt, I read the amount even equal to 3? And the new buffer has not been changed, that is, before the implementation of FLUSHRX, RX FIFO should be empty, and the last END RX interrupt, since the FIFO certainly no cache, should not return amount = 0?

1、According to my understanding, I should have been notify DMA buffer has overflowed, and then I go to use TASK_FLUSHRX instructions, but I really want to see a similar interrupt or event? Did i miss something?

2、But when I send 12 bytes to the UARTE instead of 3 bytes, the final END RX can be successfully returned amount = 2, that is, FLUSH function normal work.If the DMA buffer does not overflow, the implementation of FLUSHRX will be a problem?What is the way I know if the current DMA buffer overflow?

[Sigurd]

Hi,

You should get a EVENTS_ENDRX event when it has filled up the RX buffer. For every byte received, you should get a EVENTS_RXDRDY event. After you trigger the TASKS_FLUSHRX task, you should get a EVENTS_ENDRX event.

To make sure that this data does not overwrite data in the RX buffer, the RX buffer should be emptied or the RXD.PTR should be updated before the TASKS_FLUSHRX task is triggered.

Note that when you are using the UARTE, the .PTR and .MAXCNT registers are double-buffered.

See this infocenter page for more information: infocenter.nordicsemi.com/.../uarte.html

[Stayhungry]

Thanks,Sigurd.

I have seen this information, but I have some problems.

1, if the RX FIFO does not have data, which means no overflow,and I use TASK_FLUSHRX, then in the next EVENTS_ENDRX interrupt read .AMOUT get what? I found that it was the last EVENTS_ENDRX value, not 0. This is a normal situation, or is my operation wrong?

2, I use the hardware flow control, according to S132_SD_v5.0 82 pages, PostProcessing typical 90us, assuming that at this time I use 1M baud rate uarte to receive data (a byte about 10us), due to uarte interrupt by Softdevice timing- critical preemption, then there will be 2 bytes into the RX FIFO (6byte RX FIFO Size - 4byte RTS deactivated), ble_uart_app there are ways to deal with these two bytes?Because in ble_app_uart, I did not find the function associated with TASK_FLUSHRX.