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Using Optimisation in nrf51 Keil

Hi, I have the following piece of code.

nrf_gpio_cfg_output(PIN_EN_BSTR);

for(int i=0;i<300;i++)

{

	nrf_gpio_pin_clear(PIN_EN_BSTR);

	__NOP();

	__NOP();

	__NOP();

	__NOP();

	__NOP();

	__NOP();

	__NOP();

	__NOP();

	__NOP();

	__NOP();	

	nrf_gpio_pin_set(PIN_EN_BSTR);

	nrf_delay_us(100);

}

nrf_gpio_pin_clear(PIN_EN_BSTR);

With Optimisation level O0, the off time is 2usec and with O3, the off time is 1.4usec. Will __NOPs have different cycle time for different optimisation levels? I thought they should be the same? Thanks.

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  • __NOP() can be optimized by compiler, instead use inline assembly instructions that you can find in nrf_delay.h

      __ASM volatile (
           " NOP\n\t"
           " NOP\n\t"
           " NOP\n\t"
           " NOP\n\t"
           " NOP\n\t"
           " NOP\n\t"
           " NOP\n\t"
           " NOP\n\t"
           " NOP\n\t"
           " NOP\n\t");
    

    Inline assembly is not optimized.

  • I tested it myself on nRF51

    int main(void)
    {
    nrf_gpio_cfg_output(11);
    
        while(1)
    
        {
    
            nrf_gpio_pin_clear(11);
            nrf_gpio_pin_set(11);
    
        }
    }
    

    with -O0 it is 0.36us
    with -O3 it is 0.12us

    considering 1 cpu cycle is 0.062us I think it is doing excellent job with -O3 only two cycles and with -O0 it is taking 6 cpu cycles which is reasonable because of many debug NOPS and unoptimized reads and writes.

    inside the nrf_delay_us you also have C logic to to compare if number_of_us is positive or not, this compare logic will generate different type of code with different optimization level and will run in a loop to the number of us you give in the argument. I am not sure if we can create a software emulated delay accurate to nano seconds at different optimizations.

    I Suggest you use hardware timer for it.

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  • I tested it myself on nRF51

    int main(void)
    {
    nrf_gpio_cfg_output(11);
    
        while(1)
    
        {
    
            nrf_gpio_pin_clear(11);
            nrf_gpio_pin_set(11);
    
        }
    }
    

    with -O0 it is 0.36us
    with -O3 it is 0.12us

    considering 1 cpu cycle is 0.062us I think it is doing excellent job with -O3 only two cycles and with -O0 it is taking 6 cpu cycles which is reasonable because of many debug NOPS and unoptimized reads and writes.

    inside the nrf_delay_us you also have C logic to to compare if number_of_us is positive or not, this compare logic will generate different type of code with different optimization level and will run in a loop to the number of us you give in the argument. I am not sure if we can create a software emulated delay accurate to nano seconds at different optimizations.

    I Suggest you use hardware timer for it.

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