voltage divider/pull up resistor and current leakage !!

[Tizana]

hi,

i'm designing a custom board and i want to detect when the USB is plugged in. the nrf51822 chip working with 2.5V, for that i had the idea to make a voltage divider with two resistors and use this voltage as input. normally the value of these resistors should be as high as possible in order to reduce the leakage current.

Questions ..

1/ how high should be the resistor's value ? is there any limits ?

2/ if the divider is not that accurate and give me a value slightly different from 2.5v, let's say 2.2V , would the nrf detect this voltage as a high level ?

3/ do you think i should use a CMOS transistor to detect the usb presence better than the voltage divider ?

i have the same problem with the the pull up resistor value, i don't know exactly the resistors values that i should put in order to limit the current leakage. for example in the image the STAT signal have two stats, low and high-Z. can i put 1 Mohm or more like 10 Mohm, what are the limits ?

thx,

[RK]

1. The resistors should be 'high enough' to give not too much leakage current but not comparable to the input impedence of the chip. I'd probably use something like 47k (in fact I did just use 47k in a design of mine). That gives you leakage of 50uA which is pretty small. If you get too close to the input impededence of the chip then that resistance ends up in parallel with one leg of your divider which throws it off.

2. look at the data sheet, that will give you the max voltage which could still be seen as a zero and the min voltage which will definitely be seen as a 1. You want to make sure your '1' voltage is above that limit and below the Vdd, so aim your resistors to be 1/2 way into the '1' range.

3. no

[bjorn-spockeli]

@tizana: You can also take a look at this blog post, which explains how to use a voltage divider to measure the voltage of a LIPO battery.

[Tizana]

@Bjørn , thx for the link but the voltage divider for ADC input is different from an digital input,

for ADC the input impedance is between 100k to 400k when sampling and for the digital output that i want to make the impedance is more much higher, so this is why i ask the limitation of the voltage divider. i want to put a resistance as high as i can to limit the leakage current, but i don't know how much i can put. for example R3 = R4 = 10M is ok ?

[Tizana]

and for the voltage divider that i don't have to use the capacitor for the ADC divider ?

[bjorn-spockeli]

Yes, you can disregard the cap used in the ADC divider. You'll have to do the math, i.e. 4.5 V * (R1/(R1+R2)) = 0,7*VDD ( Min voltage seen as a logic '1' )