Altering QSPI Address Mode?

[Fan Jiaming]

I have recently acquired a NAND chip from Micron and would like to use it for storage.

However, looking through the datasheet I found out that the addressing scheme require by the Micron chip is a bit different from the QSPI used in the SoC.

For READ, READ2O and READ4O, the pattern of the address bytes following the command byte are the same for the chip and the SoC, but for READ2IO and READ4IO, they are different.

SoC QSPI:

Micron chip:

Notice how the address required by the Micron chip is only 12 bits + 3 dummy bits. The same behavior goes for the write as well.

Is there a way to overcome this so that I can use IO operation instead of O on the chip?

[Hung Bui]

Hi Fan,

I afraid it's not possible with QSPI to talk to the Flash. Here is a quote from our developer: "My initial idea was to shift the address to the left by 8 bits and make the unused least significant byte the dummy byte. However, we cannot configure our IP with zero dummy bytes."

What you can do is to use normal SPI to you have full control of what should be transmitted. We may have more improvement with QSPI in our production version of nRF52840 but it's not ready yet.

[Mickael]

Hi Hung Bui,

Do you know if thar QSPI limitations has been planned to be solved in the coming new silicon release? Supporting MICRON NAND Serial Flash would surely be a very big plus for the MCU...

Thanks for the help, Mickael