nRF24L01+ timing diagram

Hello, I am trying to implement a Time-On-Air measurement with two nRF24L01+. I set up the devices to work at 2Mbps, 3 bytes address, 1 byte payload, 1 byte CRC. Both works with dedicated 16Mhz crystal. I am using a Logic analyzer with 25Mhz sampling for my tests.

First thing, I attempted to measure time delay between CE (rising edge) and IRQ (falling edge) (packet sent) on the transmitter device. I measured a minimum delay of 156.24 us, a maximum delay of 156.36 us. Those values are both smaller, compared to what the timing diagram in the datasheet "7.7 Enhanced ShockBurst Timing" says. The calculation, according to the formula in table 19, results in 164.5us, or 160us if I suppose that there is no 9bit packet control field.

Are the diagram and the formula correct? Is it true that Tstdby2a starts at the rising edge of CE and not after 10us?

Are those times fixed? Or how much can they vary? I suppose the internal processor runs at 16Mhz, then the variation should be a multiple of related period.

Of course my final scope is to measure the delay on the RX device. In the datasheet at page 43, figure 16, it looks like IRQ on the RX device is triggered Tirq after the end of the transmission. That is, with negligible distance between TX and RX, IRQ on the TX device should happen at the same time with IRQ on the RX device. But that's not the case, there's an average delay of 5.5us between them. Again, what is the variability of these times on the RX device?

Is there another product with similar capabilities and "deterministic" timing?

Thanks a lot for your help.

  • Hi,

    The timing of the transmitter is set as according to our specification and will not vary. The PLL start up time will be 130 us (Tstdby2a), and each bit will be 0.5 us in 2 MBit mode. Using 3 byte address, one byte payload, one byte CRC; this will give you a total time of:

    130 us + (1 byte Preample + 3b address + 1 b payload + 1 b CRC)*8/ 2MBIT = 130 + 24 us = 154 us.

    The delay that you are measuring is off due to the logic that fires up the radio (setting CE and waiting for IRQ to assert). You should hold the CE pin active for at least 10 us to be certain that the radio starts up. If you have a lot of capacitance on this pin, you will see a slope before reaching a logical defined level '1', which is one of the reasons that we recommend this timing on the CE pin.

    The jitter of all clock operations are directly derived from the 16M xtal. Meaning that the 2.4 GHz signal will have the same jitter as your clock source (lets say; 40 ppm including aging and temperature tolerance)

    Best regards, Håkon

  • Hello, thanks for your answer. I will scope carefully the CE pin then.

    The delay that you are measuring is off due to the logic that fires up the radio (setting CE and waiting for IRQ to assert).

    From what you say, I understand that the code inside the nRF24l01+ can take a different amount of 16Mhz clock cycles, in order to poll CE and to set IRQ. However in your calculation you did not not include the Tirq time of 4us which is what makes my measurement so far from the calculation.

    Is it the same on the RX side? Is it true that if do an adequate number of measurements I can probably spot the "lowest execution time"? Or are there some numbers, like what are the minimum and maximum execution times for TX and RX, in addition to the 154us you calculated? Thanks again, best regards