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Retain 32 bits across a watchdog reset ?

I'm sure the same question has been asked in a few different forms, but hoping for some ideas. . . Is there a way to retain 32 bits of information across a watchdog reset ?

I currently use PPI to clock a 32 bit counter at 1Hz from the RTC, this is nice because it gives me a real time clock time in a 32 bit register that runs in low power mode (why oh why is the rtc timer not 32bit ?!?!?!?! or at least has a 32 bit prescaler)

Anyway, the problem with this is that a watchdog reset clears the peripherals, so I lose the 32 bit count. I could write the value to NVM in the watchdog event handler, as long as the flash memory was erased at program startup otherwise it would take too long, but this doesn't seem like an elegant solution.

I know that the ram is not specifically reset, but may be corrupted, to this is also a possibility I guess.

Any suggestions appreciated! Thanks

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  • Well you could push your 32 bit register to flash between watchdog refresh cycles. Unless your watchdog time is unusually short this shouldn't use much power. Then on reboot you can look for the data and load if available. At worst you will be off by one watchdog cycle. The reality is you would always be off a little on a watchdog reset since the RTC won't be configured on reset.

    As for the RTC timer, a second of 32768 fits nicely in 16 bits so even 24 bits is overkill let alone 32 bits. Don't know if they had a reason for it though.

    According to the spec, ram does not reset under any circumstance. They warn that it could be corrupted depending on the reset reason (eg, brownout). So, you could just write the 32bit word to ram once a second and just make sure to not initialize the variable in C. Sounds silly, but it should work.

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  • Well you could push your 32 bit register to flash between watchdog refresh cycles. Unless your watchdog time is unusually short this shouldn't use much power. Then on reboot you can look for the data and load if available. At worst you will be off by one watchdog cycle. The reality is you would always be off a little on a watchdog reset since the RTC won't be configured on reset.

    As for the RTC timer, a second of 32768 fits nicely in 16 bits so even 24 bits is overkill let alone 32 bits. Don't know if they had a reason for it though.

    According to the spec, ram does not reset under any circumstance. They warn that it could be corrupted depending on the reset reason (eg, brownout). So, you could just write the 32bit word to ram once a second and just make sure to not initialize the variable in C. Sounds silly, but it should work.

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