Retain 32 bits across a watchdog reset ?

[Hein]

I'm sure the same question has been asked in a few different forms, but hoping for some ideas. . . Is there a way to retain 32 bits of information across a watchdog reset ?

I currently use PPI to clock a 32 bit counter at 1Hz from the RTC, this is nice because it gives me a real time clock time in a 32 bit register that runs in low power mode (why oh why is the rtc timer not 32bit ?!?!?!?! or at least has a 32 bit prescaler)

Anyway, the problem with this is that a watchdog reset clears the peripherals, so I lose the 32 bit count. I could write the value to NVM in the watchdog event handler, as long as the flash memory was erased at program startup otherwise it would take too long, but this doesn't seem like an elegant solution.

I know that the ram is not specifically reset, but may be corrupted, to this is also a possibility I guess.

Any suggestions appreciated! Thanks

[Hein]

Also, because the RTC is 24bit with a 12bit prescaler, you cannot really use it to keep real time for years. At maximum values, it would overflow every 24 days or so if my quick math is correct. This means to do a low power timebase that runs for years, I had to use the PPI to clock a 32 bit counter every second, which then also turns on the HF clock briefly at every event, which causes a extra 100nA or so on average of extra power consumption in sleep mode. This problem could have been avoided by either being able to use the 32k clock for a 32bit timer or by making the RTC 32 bit.