NRF52840 PMU details

[Mickael]

Hi there,

I was trying to understand "sleep" power modes of the chip (CPU + Peripherals) in a bit more details - but my understanding is that everything is handled by the PMU unit and is somewhat "abstracted" from the user implementaiton. Is that correct?

However, is there a document somewhere that sets out some of the concept of this block? Or is it a complete black box? Are there coding/configuration guidelines to make sure the PMU operation will actually be optimal? Is there some registers we can read to get a feel for that peripheral is active at some specific points of our application?

Thanks for your help, Mickael

[haakonsh]

Hey Mickael,

The 'PMU' is a complete black box with the following settings; DCDC0 ON/OFF + output voltage, DCDC1 ON/OFF, System ON, System OFF, and RAM retention. 
This black box monitors the status of the CPU and each peripheral and adjust the regulators for optimal performance for any given system state.

When the ARM CPU is put to sleep(System ON) with the WFE instruction the MPU will automagically adjust the regulators. This is also true when the CPU is woken up, a peripheral is enabled/disabled, or when you enter/exit deep sleep(System OFF). 

Cheers,

Håkon.

[Mickael]

Hi Haakonsh,

one additionnal question on this front:

is DCDC1 ON/OFF only controlled by the register setting? Or does the PMU decide to revert back to LDO when in very low power state? For example, in SYSTEM OFF is DCDC1 still enabled? 

Mickael

[haakonsh]

DCDC will operate in 'refresh' modes when in a low power state. The regulator will wake up periodically to top off the supply. 

[Mickael]

thats clear - thanks again Hakon.