HI there,
I read somewhere here that the SPIM3 bus would be capable of 32MHz operations in the "next" chip revision (that was 6 months ago).
Could you confirm that it is now the case with the Engineering Sample B?
Thank you,
Mickael
HI there,
I read somewhere here that the SPIM3 bus would be capable of 32MHz operations in the "next" chip revision (that was 6 months ago).
Could you confirm that it is now the case with the Engineering Sample B?
Thank you,
Mickael
Hi,
The SPIM3 is present for engineering B, but it has these erratas:
RX buffer error at 32 MHz operation
SPIM3 does not generate EVENTS_END and halts if suspended during last byte
SPIM3 events incorrectly connected to the PPI
The first one is the most crucial for 32M operation, effectively limiting the operation frequency down to 16M. You should have engineering C if you need to evaluate 32MHz SPI operations.
For Engineering C, the errata #189 "RX buffer error at 32 MHz operation" is fixed, as shown in this section of the errata document:
Cheers,
Håkon
Super thorough answer - Thanks a lot you, Hakon.
Super thorough answer - Thanks a lot you, Hakon.