This post is older than 2 years and might not be relevant anymore
More Info: Consider searching for newer posts

Use SAADC Limit to clear GPIO via PPI

Hello,

I'm attempting to use a high-limit reached event from the SAADC to trigger the clearing of a GPIO. My wish is to disable this GPIO with the lowest possible latency, avoiding the need for the CPU to manually clear the pin. However, my current technique isn't working. Below is the code I'm using to set up the PPI:

 

Fullscreen
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
// Allocate a PPI channel
errCode = nrf_drv_ppi_channel_alloc( &mMotor.ppiChannel );
require_noerr( errCode, exit );
// Create task to clear GPIO
nrf_drv_gpiote_out_config_t config = GPIOTE_CONFIG_OUT_TASK_LOW;
errCode = nrf_drv_gpiote_out_init( mMotorConfig.enablePin, &config );
// Setup PPI channel so motor enable is immediately cleared when current limit is hit
errCode = nrf_drv_ppi_channel_assign( mMotor.ppiChannel, nrf_saadc_event_address_get( NRF_SAADC_EVENT_CH0_LIMITH ), nrf_drv_gpiote_out_task_addr_get( mMotorConfig.enablePin ) );
require_noerr( errCode, exit );
// Enable GPIO task
nrf_drv_gpiote_out_task_enable( mMotorConfig.enablePin );
// Enable PPI channel
errCode = nrf_drv_ppi_channel_enable( mMotor.ppiChannel );
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

I should also not that I've confirmed that the SAADC is being configured correctly and the high limit is being hit. Any help here would be appreciated. Thanks!

  • Why do you want to use the SAADC instead of the COMP or LPCOMP peripherial? The SAADC must be kept running and sampling all the time, which implies significant current consumtion.

  • I do not see any particular reason why this should not work, what SDK version are you using and can it be that the SAADC event is already set?

  • That was an oversight on my part. We were also logging values from the SAADC for debug purposes, but for a release solution, the COMP/LPCOMP is the right call. This worked perfectly. Thanks!