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sd_flash are events scheduled or interrupts?

Are sd_flash events NRF_EVT_FLASH_OPERATION_SUCCESS and NRF_EVT_FLASH_OPERATION_ERROR  actual events, schedule and only run when app_sched_execute is run.  Or are they run from and interrupt handler.

Basically, is the NVM event handler run in and interrupt handler?

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  • Hi Jordan,

    The sd_flash_* API is a scheduled operation, which will be queued by the application and executed at a later point, in-between your bluetooth events, so that your connection(s) is "the least disrupted". You'll then get a event back to the application with either _SUCCESS or _ERROR from the SoftDevice-handler.

    More info on how the softdevice handles these events are described here:

    http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.s132.sds/dita/softdevices/s130/processor_avail_interrupt_latency/flash_usage_patterns.html?cp=2_3_1_0_15_2_0

    Why does the softdevice handle flash operations?

    It is mainly because the hardware peripheral for flash erase or write will halt the CPU when it's on-going. In this sense, you can look at the NVMC-peripheral as a blocking interrupt, which will halt the CPU until the flash operation is finished. Any pending event occurring while the flash-operation is on-going will be handled afterwards, like a TIMERx event or a UART_RX event. This is because peripherals runs independent of the CPU state. This is similar for a normal debug session, where you halt the CPU, but all enabled peripherals still runs (timer keeps counting, rtc keeps ticking, etc.)

    As a historical aspect, early versions of the first SoftDevice (back in '11 or '12, for the nRF51-series) did not handle flash operations in the stack, so the application needed to do this when a connection-interval was finished. However, this might cause timing-errors if you used a lower connection interval, like 7.5ms, and triggered an _ERASE operation. The flash operation handling was therefore moved to the stack, so that it could handle such a scenario in a more graceful way, and not cause assertions in the application for tight timing scenarios.

    The hardware peripheral that triggers flash operations is the NVMC, which you can read about here:

    http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/nvmc.html?cp=2_1_0_10#concept_pcl_wbz_vr

    Cheers,

    Håkon

Reply
  • Hi Jordan,

    The sd_flash_* API is a scheduled operation, which will be queued by the application and executed at a later point, in-between your bluetooth events, so that your connection(s) is "the least disrupted". You'll then get a event back to the application with either _SUCCESS or _ERROR from the SoftDevice-handler.

    More info on how the softdevice handles these events are described here:

    http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.s132.sds/dita/softdevices/s130/processor_avail_interrupt_latency/flash_usage_patterns.html?cp=2_3_1_0_15_2_0

    Why does the softdevice handle flash operations?

    It is mainly because the hardware peripheral for flash erase or write will halt the CPU when it's on-going. In this sense, you can look at the NVMC-peripheral as a blocking interrupt, which will halt the CPU until the flash operation is finished. Any pending event occurring while the flash-operation is on-going will be handled afterwards, like a TIMERx event or a UART_RX event. This is because peripherals runs independent of the CPU state. This is similar for a normal debug session, where you halt the CPU, but all enabled peripherals still runs (timer keeps counting, rtc keeps ticking, etc.)

    As a historical aspect, early versions of the first SoftDevice (back in '11 or '12, for the nRF51-series) did not handle flash operations in the stack, so the application needed to do this when a connection-interval was finished. However, this might cause timing-errors if you used a lower connection interval, like 7.5ms, and triggered an _ERASE operation. The flash operation handling was therefore moved to the stack, so that it could handle such a scenario in a more graceful way, and not cause assertions in the application for tight timing scenarios.

    The hardware peripheral that triggers flash operations is the NVMC, which you can read about here:

    http://infocenter.nordicsemi.com/topic/com.nordic.infocenter.nrf52832.ps.v1.1/nvmc.html?cp=2_1_0_10#concept_pcl_wbz_vr

    Cheers,

    Håkon

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