According to the nRF51 series reference manual. 10.1.2 Debug interface mode
Debug interface mode is initiated by clocking one clock cycle on SWDCLK with SWDIO=1. Due to delays caused by starting up the DAP's power domain, a minimum of 150 clock cycles must be clocked at a speed of minimum 125 kHz on SWDCLK with SWDIO=1 to guaranty that the DAP is able to capture a minimum of 50 clock cycles.
The clocking speed for this phase is a minimum of 125kHz. What is the maximum speed? Or is that a typo and 125kHz is actually the maximum speed?
Thanks