nrf52840 Rev 1 Errata DCDC Reg0 not working at all?

[Florian Zierer]

Hi,

I just saw the errata for the nRf52840 Rev 1 and it seems Anomaly 197 (DCDC of REG0 not functional) and 202 (Device does not start up in high voltage mode) make it impossible to use the High voltage DCDC mode.

Is there any way to make use of the DCDC? Of course the LDO can be used to circumvent 197 but what about 202? At system startup it is nearly impossible not to draw any current if there is external circuitry connected!

We have chosen the nrf52840 especially for this feature (internal DCDC) to remove as much external (e.g. DCDC) components as possible.

Is there any updated chip revision planned to fix this bug?

In fact right now a guaranteed feature is missing completely!

[Kenneth]

Hi,

If you require to support external circuitry (VDD from REG0) then you can't use DCDC on high voltage mode (VDDH) no. You can use LDO mode instead, with the power penalty that may give compared to DCDC, depending on the voltage difference between VDDH and VDD.

You should ensure that VDDH rise time is <1ms and that you have a gpio to control a mosfet to ensure VDD from REG0 is not powering external circuitry by default after reset.

 

[Florian Zierer]

Hi Kenneth,

this is really bad news for us. LDO vs DCDC is an efficiency problem (not good but at least it should work for now), but the external circuitry issue would be a show stopper!


One important question for us.

In the Revision Engineering A the supply of external circuitry was working. The errata does not mention this issue and on our testboard with a Rev A IC the startup and supply seem to work.


Was there really a degression from A to B or was it just that you increased some testing or some limits?

If the silicon behaves for external circuitry like Rev A, our schematics and layout should work.

[Kenneth]

This issue have been partially masked by other issues that prevented low power mode when using VDDH for previous revisions. There is also more testing involved now where this problem was discovered.

Make sure to follow the schematic and layout for final hardware revision 1.

[Atlas]

Hi

In errata v1 - 3.29

- Symptoms : VDD voltage drop below specification when entering low power modes. Low voltage may trigger reset of device.

Conditions : Using DCDC on REG0, high voltage mode. DCDC on REG1 is not affected.

I don't use DCDC and want to use REG0 to set VDD output 1.8V in high voltage mode.

Does it trigger reset of device?

Thanks.

Atlas

[Kenneth]

You should also see Errata-202 that apply to using REG0 with LDO or DCDC: "Do not draw current from VDD pin (external circuitry supply) during power up and ensure VDDH rise time is below 1 ms."

Note that there is currently an on-going discussion to fix both Errata-197 and Errata-202, I will know more in a few days.