MCLK jitter

[DBT]

Chapter 43 of the OPS document for the nRF52840 says that the I2S interface has a "Low-jitter Master Clock generator" but I don't see a jitter spec for it.

What is the MCLK jitter spec?

[MartinBL]

Hi,

Due to the Easter holiday the support staffing is reduced. Most likely, there will not be any response to this case before week 14.

Best regards,
Martin

[DBT]

Its after Easter now.  Is someone looking at this?

[haakonsh]

Hey Douglas,

Sorry for the long wait, we still have some kinks with the new support portal that we need to iron out.

The MCK is derived from either the 64 MHz internal oscillator (HFINT) or the 64 MHz crystal oscillator (HFXO). The ultimate jitter will also be determined by the LRCLK. See Table 1. Configuration examples in the Master clock (MCK) chapter. 

Cheers,

Håkon.