Hello !
I have a big problem !
I explain : am using the NORDIC nRF52840 board (as slave), to answer to a microcontroller (the master), using SPI. My nRF52840 has to simulate an accelerometer and to answer to each request of the microcontroller. So each SPI transaction sent by the microcontroller contains 2 bytes of 8 bits, sent on the MOSI line : the first byte contains the address of the register the microcontroller wants to read in OR write to (on 7 bits) and the bit read/writeNOT.
The second byte is sent instantaneously after the first, and contains eventually the value to store in that register; or the slave should eventually clock out the value contained in the register (on the MISO line) simultaneously with this second byte.
My question is : if the microcontroller wants to do a READING operation : the nRF52840 should receive the first byte from the microcontroller, analyze it, find the value contained in this register (I represent a register by a single uint8_t variable), and clock it out simultaneously with the second byte sent by the master. But after some research I realized it cannot be done (at first glance), since the RX and TX buffers cannot be modified between the two interrupt events : NRF_DRV_SPIS_BUFFERS_SET_DONE and NRF_DRV_SPIS_XFER_DONE .
I took a look in the nRF datasheet in the SPIS chapter, where I saw that a flag can be activated : the EVENTS_ENDRX, whose goal is to generate an interrupt when the buffer RX has been entirely filled. My idea was thus to activate this flag and to use an RX buffer of size 1 so that I’m warned at the moment where the first byte of the transaction has just been sent. At this time normally I would have to modify the TX buffer AND get it READY just before the transmission of the second byte of the SPI transaction.
I also saw some interesting figure in the nRF datasheet : “Figure 82: SPI transaction when shortcut between END and ACQUIRE is enabled”. This seems to explain that, an SPIS semaphore is owned by the spis_module during SPIS transaction, and cannot be acquired by the CPU until SPIS transaction is finished. And it is described that any RX- or TX-buffer modification requires this semaphore to be owned by the CPU ! I think my project will end here, but maybe someone will save me !
Is there any way to modify the TX buffer during an SPIS transaction ? Thanks a lot for your help.
