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nrf24lu1 interrupt latency

I am trying to create a TDMA based network with the nRF24LU1+. I understand that nRF51 and nRF52 have the ability to trigger the transmission of a radio packet upon timer event using GPIOTE, but this does not exist on the nRF24LU1+. Because of this, I am looking at using a timer interrupt to generate a high pulse on the rfce bit in the RFCON register (SFR 0x90 bit 0).

What is the interrupt latency on the embedded 8051 in the nRF24LU1+? How is it bounded? I can set the timer interrupt to a high priority but this is only part of the picture in implementing a stable TDMA system without GPIOTE.

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  • Thank you @kenneth. It looks like I should be able to set up a timer interrupt as the highest priority and then flip the bit with very little context switching (saving registers) overhead. If I'm reading correctly, though, it looks like there could be significant (relatively speaking) jitter since the 8051 core used on the nRF24LU1 can take up to 6 cycles (375ns @16MHz) to execute an instruction and I am sure the core will finish executing its current instruction before branching to an ISR.

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