nRF52840 Maximum I2S Settings

[rpriddell]

I had planned on using the nRF52840 I2S peripheral in Nordic Master mode to either produce a 31.25 kHz sampling rate, or a 62.5 kHz sampling rate for my application.

 There seems to be a discrepancy in your datasheet. Looking at the V1.0 spec, on Table 50: Configuration Examples  we see an example showing how one can hit 31.25 kHz from the 64 MHZ clock which involves using an 8 MHz MCLK. Then in the electrical specification 6.11.11 section it says the maximum MCLK you can use is 4 MHz. Furthermore it says 48 kHz is the max LRCLK and 2 MHz is the faster SCK. Are these maximums in error? The MCLK ratio register defines MCLKS up to 10 MHz, Nordic’s own example shows using an 8 MHz MCLK, but the timing specifications say you can’t go above 4 MHz.

Also my 62.5 kHz setting would be violating the 48 kHz LRCLK maximum listed, even though it meets Config.Ratio >= 2*Config.SWDITH, SCK < MCLK,  and that ConfiG.Ratio / (2*Config.SWIDTH) must be an integer rules.

My proposed settings would be (based on an external 32 MHz HF crystal being used to produce the 64 MHz internal clock):

MCLK: 4 MHz

Config.Ratio =  128

Config.SWIDTH = 16

Producing an SCK of 1000 kHz

Producing an LRCLK of 31.25 kHz

 

Or

 

MCLK: 8 MHz

Config.Ratio =  128

Config.SWIDTH = 16

Producing an SCK of 2000 kHz

Producing an LRCLK of 62.5 kHz

 

I’m not sure why this wouldn’t function for any reason other than the datasheet warns against MCLK above 4 MHz and frame clock above 48 kHz. Can you advise if this would be acceptable?

[rpriddell]

I should also note that my application would be I2s format mono, not stereo. 

[rpriddell]

One further datapoint to add... I would only be interested in the nordic master receiving data over I2S and do not need the transmit path to work. So if there is some restriction on Master TX, i needn't be concerned.

Nordic as Master, I2S Format, Mono, Nordic Rx only (no transmit needed), 62.5 kHz frame clock with 8 MHz master clock desired, 16 bit width.

[haakonsh]

Hey massimo,

4MHz is the limit for MCK. The MCK is derived from the 32MHz clock and a divisor. In the SDK example the default config is 32MHz /8 = 4MHz.

 

Cheers,
Håkon H.

[haakonsh]

4MHz is the specified limit, even when operating in slave mode.

[rpriddell]

What drives this though? The configuration examples and register settings indicate you can use a divisor smaller than 8. Empirically I can set it up with a divisor producing an MCLK of 8 MHz and I see no issues on the clock edges. Is this a true limitation, or is there lack of production testing to verify it will work?