Our application needs to read 128 bytes from 6 SPI sensors as efficiently as possible. We're currently using a single SPI Manager to read all 128 bytes from all 6 sensors. We're reading the 128 bytes every 1 ms, all works fine with a SPI clock of 2 MHz. The 6 sensors are read sequentially via the SPI Manager by using the pre and post callbacks to toggle the various SPI chip select lines as needed.
Since we're running all the sensors sequentially, it means there is a bit of lag between when the first sensor is read to when the last sensor is read. Ideally, we could read all 6 sensors in parallel, so that all of their data is captured at (almost) the same time. Obviously, this is not possible, but we're wondering if using additional SPI Managers would help minimize the lag between sensors, or if we've going to run into memory bandwidth or processor problems.
We plan to do some testing shortly, but was wondering if there's any data available that might help us in our testing? I could not find any data on the practical limits of number of SPI managers vs. the SPI clock rate vs SPI thru put. Are there other parameters we can tweak? Is 4 SPI managers really the limit? We have some flexibility on splitting up the sensors, so divvying up the sensor data among SPI managers is not a problem.
Any comments, links, or suggestions are appreciated. We're probably a few weeks away still from starting this tuning, but wanted to start thinking about ti now.
Ed
