SPIS data shifting

[arikyang]

I am testing SPIS to transmit mass of data(255 bytes each call) from nrf5 DK.

I found SPIS data shifting randomly.

The testing data is 0x88 but sometimes can get 0x44.

Below is correct logs.

This is the wrong wave.

When I turn on the Log, SPIS data is always correct, randomly got 0x44 when RTT log is off.

I make sure "USE_DMA_ISSUE_WORKAROUND" is ON and csn_event_handler() is entering.

Anything else I can fix or workaround this issue?

[ovrebekk]

Hi

What clock frequency is the SPI running at?

Have you made sure to select the correct SPI mode (clock polarity and phase) both on the master and slave side?

Best regards
Torbjørn

[arikyang]

2MHz

Yes, both sides are setting 0 mode.

I think SPIS peripheral is not response CS low quickly, sometimes MISO is still keeping HIGH when CS low and the clock has shaken.

The frequency roll down to 600KHz is more stable as my workaround.

[ovrebekk]

Hi

Have you measured the delay between CSN going low and the first bit being clocked out on the bus?

Is the CPU on the slave side in sleep mode before the SPI interface is activated?

As you can see in the specification there are some limits on how small the delay between CSN going low and the data being sent can be, depending on the power down mode used. 

Also, what is the length and type of the SPI signal wires? 
Do you have two devkits connected, or have you made custom hardware with signals on the PCB?

Best regards
Torbjørn

 

[Turbo J]

Did you read chapter 32.6.2 "Serial Peripheral Interface Slave (SPIS) timing specifications"?

The SPIS needs a delay of 1000ns from the CS low transistion to the first CLK pulse - in CONSTLAT mode.

In low power mode this is even longer, since the HFINT oscillator must start up first.

[arikyang]

Have you measured the delay between CSN going low and the first bit being clocked out on the bus?

- no,  haven't chance to measure.

Is the CPU on the slave side in sleep mode before the SPI interface is activated?

-Where can I know if CPU is in sleep? There is the idle_state_handle() in the main loop. Is that mean CPU will go to sleep?

As you can see in the specification there are some limits on how small the delay between CSN going low and the data being sent can be, depending on the power down mode used. 

- The problem is SPIM is in another system which I cannot code a delay between CS and clock.

Also, what is the length and type of the SPI signal wires? 
Do you have two devkits connected, or have you made custom hardware with signals on the PCB?

- It is two dev kits jump wires each other about 10cm.