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SPIS High power consumption

I'm using the SPI in slave mode and have a very high power draw: > 2 mA. The issue happens both in my application + custom board as well as with the dev-kit + SPIS example code in the SDK. I'm using SDK 12.3.

When the SPIS peripheral is initialized and enabled power is as expected: about 17 uA on the dev-kit. When the Chip select goes low, power jumps to about 2.15 mA. I'm not clocking in data, eg SCK is idle. The CPU is still sleeping the entire time.

I am guessing  the HCLK is being enabled to max speed: when I switch to DCDC mode power is reduced to 1.1mA.  However, the datasheet states power consumption is 45 uA typical run current.

No pullup on CS. I am using the default IOs in the SPIS example and use P0.31 as a GPIO to toggle the CS. Other than that, I am using the SPIS example in it's default form.

Enabling or disabling constant latency mode does not help.

What could this be?

Thanks,

Dirk

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  • Hi Dirk,

    The DMA mechanism itself has a significant current consumption of about 1.2 mA for the nRF52832. This is independent of the specific peripheral, and not counted in the electrical specification for the SPI peripheral (or any other). Please note that using DMA still improves the overall current consumption compared to not using DMA in most cases, as the nRF will be able to complete the transaction quicker, so that it can go to sleep as fast as possible.

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  • Hi Dirk,

    The DMA mechanism itself has a significant current consumption of about 1.2 mA for the nRF52832. This is independent of the specific peripheral, and not counted in the electrical specification for the SPI peripheral (or any other). Please note that using DMA still improves the overall current consumption compared to not using DMA in most cases, as the nRF will be able to complete the transaction quicker, so that it can go to sleep as fast as possible.

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  • Thanks Einar, that makes sense now. I can work around this by keeping the CS only active while data is being clocked in to reduce power to a minimum. 

    I have done some more digging on the forums and found that the nRF51 has a much more complete definition for power consumption. Specifically there's a chapter "8.3 Block resource requirements" in the Product Spec which makes it much more transparent what the mechanics in the SoC are doing. The nRF52 Product Spec does not contain this information.  It's possible I missed it, but I could not find any documentation at all in the nRF52 product spec regarding DMA power-usage. I read that the SPIS peripheral takes 45uA so that's the number I use in my estimations. This number is completely meaningless without the mention of DMA, especially considering the fact I HAVE to use the DMA.

    Just my 2 cents, I hope this will be considered as constructive feedback for the next nRF52 Product Spec revision.

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