Sharing SWD interface with GPIOs

[paul]

Hi Nordic,

I'm working on a project with very limited board space. I'd like to have the option for both SWD and GPIOs to share the same test points on the board. Ideally, full SWO and reset functionality would be intact. But also, those pins would be used as GPIOs for UART log output, timing outputs, and DTM. 

If I'm reading the documentation correctly, I should not connect SWDCLK to IO, and obviously not the VDD and GND pins. So I'm thinking I can simply route SWO, SWD, and the configurable nRESET pins to 3 separate GPIOs for debug use. 

Is this all correct? Thanks!

[run_ar]

Hi,

For nRF51 I would not recommend this as the chip would very easily go into debug mode unintentionally.

For nRF52 it might be possible to share the same test point as it is much harder to enter test more. if you make sure you do not try to use the swd interface at the same time as the uart/timing and DTM. Make sure you do not enter the initialization sequence as described here.