Problem with nrf51822 in spi slave mode

[Sean]

Hello all

I making some device with ARM core CPU with nRF51822.

I set CPU to SPI master and set nRF51822 to slave. And then I read some data from nRF51822, that was always "0x55" or "0xAA". That depend on configuration of POL and PHA in master side.

Do you guess what is wrong?

B. Regards,

[Stefan Birnir Sverrisson]

Hi Sean

I assume you are using the spi_slave_example from nRF51 SDK v6.0.0?

The character 0x55 is the ORC character (SPI over-read character). The character 0xAA is the DEF character (SPI default character) You can read about what those characters stand for in the SPIS section in the nRF51 Series Reference manual. I do not realize however why they are clocked out on MISO in this case.

The most common problem however when interfacing the nRF51 SPIS is that there needs to be a 7.1us delay from when you set CSN high until you start clocking out data, see nRF51822 PS v2.0, table 39.

Make sure your POL and PHA settings are identical on SPI master and SPI slave side. To configure that on the nrf51 slave, you need to write to the SPIS->CONFIG register. To do that in the spi_slave_example from nRF51 SDK v6.0.0, you select the SPI mode. By default, the example sets the SPIS to mode 0 (see the spi_slave_example_init function), which contains the configuration (CPOL = 0, CPHA = 0). The total mapping is:

SPI_MODE_0,                             /**< (CPOL = 0, CPHA = 0). */
SPI_MODE_1,                             /**< (CPOL = 0, CPHA = 1). */
SPI_MODE_2,                             /**< (CPOL = 1, CPHA = 0). */
SPI_MODE_3                              /**< (CPOL = 1, CPHA = 1). */

as defined in spi.slave.h. So, select the mode that reflects the POL and PHA settings of the SPI master device.

If the above does not help, it would be helpful to see all the signals on the SPI bus, i.e. the CSN, SCK, MOSI and MISO

[Sean]

SPI slave(nRF51) using SPI_MODE_0(fixed. I can't change this side), and I try MODE_0~MODE_3 in master side. And I provide the delay between spi_cs_enable and spi_write, also between spi_cs_enable and spi_read, also.

Master MODE_0: Write 0x33, Read: 0x55 Master MODE_1: Write 0x33, Read: 0xAA Master MODE_2: Write 0x33, Read: 0xAA Master MODE_3: Write 0x33, Read: 0xAA (Write means master to slave, Read means slave to master)

I guess give waveform on the bus lines to you in tomorrow.