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BLE SPI Master - SPI Slave -Nor flash

Murali

Hi,

I am trying to test an external nor flash(as SPI slave) with the mKit dev board (as SPI master).

I was looking at the SPI examples and a bit confused about them. I am trying to figure out, how a byte is transmitted or received. Does assigning a value to NRF_SPI_TYPE->TXD cause the data to be physically sent? How are the chip select pins set low and high in this process.

Also, in case of interrupts does, what happens to the chip select pin. (I would guess, the state of the chip select pin would determine the completeness or incompleteness of the SPI commands to the external flash)

Based on how these work, I think I would need to implement a flash memory read, write & erase operations for the external SPI nor flash. They would be mostly a bunch of SPI byte_reads or byte_writes with some glue code. But I am stuck at understanding, how the basic SPI byte read or write happens.

can anybody who has interfaced nrf51822 with external SPI flash comment about their experience or pointer to any such information or example code.

Thank You, Murali

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  • 0

    Have you read the 5-10 pages in the nrf51 Series Reference Manual documentation about the SPI interface which shows you all the registers, gives you timing diagrams, sequences etc? It starts on page 137 on my version. (Section 25).

    For instance you're asking about chip select .. from the first paragraph in the documentation

    The SPI master does not implement support for chip select directly.

    The timing diagrams for TX and RX are pretty clear and show when data is written to the chip, how it's clocked out and when it's available for read.

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  • 0

    Have you read the 5-10 pages in the nrf51 Series Reference Manual documentation about the SPI interface which shows you all the registers, gives you timing diagrams, sequences etc? It starts on page 137 on my version. (Section 25).

    For instance you're asking about chip select .. from the first paragraph in the documentation

    The SPI master does not implement support for chip select directly.

    The timing diagrams for TX and RX are pretty clear and show when data is written to the chip, how it's clocked out and when it's available for read.

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