I2C interrupts

[bvgvova]

Hi.

I have a problem to understand what is the difference in SFR registers IEN1 and INTEXP.

Bit 2 in both of them is responsible for enabling 2-Wire completed interrupt, as stated in discreption.

In addition, there is one more "enabler" - bit 5 in W2CON1;

So why this mash exists & what is the real role of each registers (bits) ?

Examples I found don't highlight  the question.

Maybe someone have a clear understanding, please..?

[Simon]

The figure below gives some insight, the registers INTEXP and IEN1[2] are marked with red. In order to use WIRE2IRQ as source for the interrupts bit 2 in INTEXP and bit 2 in IEN1 needs to be set to 1.

The register W2CON1 is concerned with configuration of the 2-Wire specifically, and the Product Specification for nRFLE1 says the following about bit 5 in that register: "Updates to the maskIrq configuration bit (W2CON1[5]) should be performed before transmission begins", and it should be assigned a value of 0 in order to enable interrupts.

Best regards Simon Iversen

[bvgvova]

Thank you, Simon.

I had red the specification, of course. Misunderstanding comes from the fact, that "enabling" registers are connected in series. I thought that there was some hidden sense..

nevertheless thanks for you reply.

Best regasrds Vladimir.