Hi,
the Nordic nRF-series SoCs have got the restriction, that the power has to rise from 0 V to 1.7 V in 60 ms for a guaranteed POR. In our application we cannot guarantee that rise-time. This is why we have to use an external supervisor IC. Normaly the output of this IC is used to connect to the reset pin of a microcontroller for a safe and guaranteed reset.
I read in the Nordic nRF52832 datasheet that the P0.21 is configured as GPIO after reset. The register PSELRESET[0] & PSELRESET[1] contain 0xFFFFFFFF after reset. This means they are configured as GPIO normally. I can write to this register, that the P0.21 is configured as reset after a reboot or reset.
1. But does this mean: Only if the chip can boot, activate CPU and load the configured values out of the flash-registers, the P0.21 is configured as reset?
2. If chip cannot boot and load the values out of that registers due to a POR failure, the P0.21 will not work as a hard reset pin?
3. If my assumption is not right, please clarify, how can the chip in hardware get the value out of its flash and connect the P0.21 to reset functionality without doing a clean power-on reset?
4. If my assumption is right, to ensure a safe circuit behavior, I have to connect a MOSFET between VDD-Bat and nRF-VDD. Then connect the gate pin of the MOSFET to the supervisor IC. Is this correct (bad solution)?
Thank you!
Regards
Andre