SPI MISO data is not reflecting on the receive buffer

[Chinna]

• • Attached the MOSI and MISO signal CRO captures. I could see the write and read data on the SPI lines. But MISO data is not reflecting on the receive buffer.

    Image1

    

    Image2

    

    The Yellow line in the above picture is MOSI and Green is MISO.

    Its is a combination of Read(Read Command + Start Address) and Write sequence (Write Enable, Write Command + Start Address, Data)

    Image 1 Data is 0x50

    Image 2 Data is 0x55

    Yellow line (MOSI) Read Command is sent followed by read address ( 24 bit address - 0x00,0x00,0x00). And response for the received command is in green (MISO) line 0x50(image1) and 0x55(image2). Reading 4 bytes of data from starting location 0x00.

    Yellow line (MOSI), Write Enable, Wrtie Command is sent followed by read address ( 24 bit address - 0x00,0x00,0x00) and four byutes of data (0x50 - (Image1), 0x55 (image2), Write status command. Response for the received command is in green (MISO) status byte . 

    Conclusion: Analysing both images, Even if write different data in the location (0x00) during the read sequnce i could see the same data (Data written in wrtie sequence) in the MISO lines but same data i am not able to capture in the receive buffer for the further processing.

    Knidly share your thoughts in the same.

    Thanks & Regards,

    Chinnasamy.

[Jørgen Holmefjord]

Hi,

Have you checked that the SPI interface is configured with the correct pin number?

Which SDK version are you using? Can you post your code showing configuration, initialization, and transfers you are doing on the SPI peripheral?

Best regards,
Jørgen

[Chinna]

• Hi Jorgen,

  I am using SDK 12.3.0, Softdevice 132.

  I am refering following link for SPI initialization:

  http://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.sdk52.v0.9.1%2Fhardware_driver_spi_master.html&cp=4_0_0_2_7

  I am interfacing M95M02 EEPROM.

  Here is the code snippet for your review.

  SPI Initialization code.

  void eepromInit()
  {
     ret_code_t err_code =0;
     nrf_drv_spi_config_t spi_config = NRF_DRV_SPI_DEFAULT_CONFIG;
     spi_config.ss_pin = SPI_SS_PIN;
      spi_config.miso_pin = SPI_MISO_PIN;
      spi_config.mosi_pin = SPI_MOSI_PIN;
      spi_config.sck_pin  = SPI_SCK_PIN;
   
     err_code = nrf_drv_spi_init(&spi, &spi_config,spi_master_event_handler);
    if (err_code != NRF_SUCCESS)
    {
      // Initialization failed. Take recovery action.
    }
    while(1)
    {    
       NVMWrite(0x100,"data" , 1);
       nrf_delay_ms(10);
      NVMRead(0x100,"data" , 1);
    }
  }

   void spi_master_event_handler(nrf_drv_spi_evt_t const * event)             
  {
      switch (event->type)
    {
     case NRF_DRV_SPI_EVENT_DONE:
      // Inform application that transfer is completed.
      m_transfer_completed = true;
     break;
     default:
      // No implementation needed.
     break;
      }
  }

  void NVMWriteEnable(bool flag)
  {  
    memset(m_rx_buf, 0, m_rx_buf_len);
    memset(m_tx_buf, 0, m_tx_buf_len);
   
    m_tx_buf[0] = (flag == 1)? 6: 4; //(flag == 1)? EEPROM_WREN: EEPROM_WRDI;
    m_tx_buf_len = 1;
    
    if(nrf_drv_spi_transfer(&spi,(uint8_t const *)m_tx_buf,m_tx_buf_len,m_rx_buf,m_rx_buf_len) == NRF_SUCCESS)
    {
     m_transfer_completed = false;
     while(m_transfer_completed == false);    
    }
  }

  void NVMWaitToCompleteExecution(void)
  {
   
    do
    {
      memset(m_rx_buf, 0, m_rx_buf_len);
      memset(m_tx_buf, 0, m_tx_buf_len);
   
      m_tx_buf[0] = 5;//EEPROM_RDSR;
      m_tx_buf[1] = 0xFF;
      m_tx_buf_len = 2;
      
      if(nrf_drv_spi_transfer(&spi,(uint8_t const *)m_tx_buf,m_tx_buf_len,m_rx_buf,m_rx_buf_len) == NRF_SUCCESS)
      {
       m_transfer_completed = false;
       while(m_transfer_completed == false);    
      } 
      if((m_rx_buf[0] & 0x01) != 0)
      {
       nrf_delay_ms(10);
      }
      
    }while((m_rx_buf[0] & 0x01) != 0);   
  }

  void NVMWritePage(uint32_t Address, uint8_t *const p_Buffer, uint32_t NrOfElementsInArray)
  {
    memset(m_rx_buf, 0, m_rx_buf_len);
    memset(m_tx_buf, 0, m_tx_buf_len);

    m_tx_buf[0] = 2;//EEPROM_WRITE;    
    m_tx_buf[1] = 0x00;  
    m_tx_buf[2] = 0x00;  
    m_tx_buf[3] = 0x00;    
    
    m_tx_buf[4] = 0x50;  
    m_tx_buf[5] = 0x50;  
    m_tx_buf[6] = 0x50;  
    m_tx_buf[7] = 0x50;    
    
    m_tx_buf_len = 4 + 4;
    
    if(nrf_drv_spi_transfer(&spi,(uint8_t const *)m_tx_buf,m_tx_buf_len,m_rx_buf,m_rx_buf_len) == NRF_SUCCESS)
    {
     m_transfer_completed = false;
     while(m_transfer_completed == false);    
    }  
  }

  void NVMWrite(uint32_t Address, uint8_t *const p_Buffer, uint32_t NrOfElementsInArray)
  {
   NVMWriteEnable(1);
   NVMWritePage(0x00,"data",4);
   NVMWaitToCompleteExecution();
  }

  void NVMRead(uint32_t Address, uint8_t *const p_Buffer, uint32_t NrOfElementsInArray)
  {
    memset(m_rx_buf, 0, m_rx_buf_len);
    memset(m_tx_buf, 0, m_tx_buf_len);

    m_tx_buf[0] = 3;//EEPROM_READ;    
    m_tx_buf[1] = 0x00;  
    m_tx_buf[2] = 0x00;  
    m_tx_buf[3] = 0x00;    
    m_tx_buf_len = 4+4;
    
    if(nrf_drv_spi_transfer(&spi,(uint8_t const *)m_tx_buf,m_tx_buf_len,m_rx_buf,m_rx_buf_len) == NRF_SUCCESS)
    {
     m_transfer_completed = false;
     while(m_transfer_completed == false);    
    }
    m_transfer_completed = false;
  }

  Thanks & Regards,

  Chinnasamy.