Possible to use nrf51822 without antenna (like simple MCU)?

[the_summer]

Hi,

I had a few nrf51822s lying around and as I find the chip and the SDK quite convenient to use, I thought about using them in a small MCU project which does not need any radio communication. This is also the first custom nrf51822 board I designed therefore I stayed very close to the reference schematic of the product specification (LDO setup). 

However, after assembling a test circuit I could not get openocd to connect to the chip (it works with a bought module). After reading several other threads here I am not sure if the unconnected ANT1/2 pins could prevent the the chip from initializing? They are currently free floating. Should I ground them or are there any components necessary for proper operation?

Best regards,

    Jan

[AmbystomaLabs]

Normally Ant1 and Ant2 DC float and are connected to VDD_PA across the output balun.  It shouldn't be required to provide power to the final stage of the radio for the MCU to fire up.  Leaving these floating should be fine.

Likely something else is wrong, such as insufficient local capacitance, too low of a supply voltage for SWD to operate, etc.

[the_summer]

Thank you, good to know. I use 3.3 V for the power supply and the SWD. I guess that should be sufficient.

I used the following schematic based on the reference circuits of the product specification. Does anyone see grave mistakes?

[AmbystomaLabs]

If you wish, post your layout and I can review/comment.

[the_summer]

Here is the bottom layer:

And here the top layer:

[AmbystomaLabs]

You have got a lot of problems with this board.  I actually just helped out someone who made similar mistakes.

For starters the caps need to be at the pins specified in the reference layout.  When you place them far away the parasitic inductance in the trace combined with crosstalk between different parts of the IC create one big mess on the supply rails.

Second you should never share ground connections. Above you share crystal load caps with general ground connections with the nRF.  All bad. There are other shared grounds, I just pointed out those.  You should always strive to have a via for each ground.  Barring that you can dump the current to the ground pour, but on your board there isn't a ground pour.

Finally, where is the ground pour?  There should be a ground pour at a minimum on the bottom layer(top layer for you since you place the nRF on the bottom) to give all the ground currents easy paths back to the origin.  Same as on #1, all the parasitics from the traces just makes for a mess on Vdd.  The ground flood should include Epad otherwise Epad isn't really doing anything.

Your via pattern on Epad is minimal and would be insufficient for RF.  But since you aren't using the radio you might not care.  I would recommend you copy the ref design 4x4 pattern.  On the devices we make we use a 5x5 pattern.  You may as well add the 3 inductors that provide power to the RF output.  Isn't much room and who knows you may decide to turn on the radio after all.  Doesn't really need an antenna for close range comms. On the Ref design this is L1, L2, C3.

Sorry, your board is really messy.

I would recommend on your schematic you make the schematic object look like the part.  When you have it as a generic box with 49 pins it invites the kind of mistakes you made since there isn't any awareness of how the layout should look when you put down the traces.  This is probably less important when it is basic logic circuits but on a complicated SoC it is very important to get the parts physically where they belong.

[the_summer]

Thank you very much for your comments. I think I have to go back to the drawing board then. I had a ground fill on both layers (they were hidden when I made the screenshot. Sorry for that), but after some additional reading I think they weren't too well connected anyways.

So far I mainly used AVRs when doing simple custom designs. I suppose they are more forgiving regarding amateurish design.

[AmbystomaLabs]

Sorry if I was overly critical.  I didn't mean to discourage you.

You mentioned there is a ground pour.  Watch out for what happened in your top layer where the traces barricade the ground pour and isolate it to essentially just the die.

Your design will be more robust if you just keep all the components on the same layer.  Then you can focus on keeping the ground pour under the SoC as complete as is possible.  This more important if you use the RF.  Then you have to have a uniform ground to launch the wavefront from.

If you wish, please post your updated layout for review before you send it out for fab.