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GPIO goes low when VDD drops, even if set for input

Greetings,

I believe I'm seeing the same issue as this DevZone ticket:  https://devzone.nordicsemi.com/f/nordic-q-a/23903/gpio-behaviour-during-power-down-nrf52832/94059#94059

We've tried setting the GPIO PIN_CNF register to 0x2 (default).  This happens to be on P0.12 in this particular case.

What was the resolution, as the issue was moved private before a solution was indicated? 

Thanks,

Bob

  • Hey Bob,

    Do you have a scope of the VDD and GPIO?

    I'll try to find the old MyPage case and see what the outcome was. 

    -Edit

    "Unfortunately, GPIO behavior may be unpredictable when VDD is very low. When the battery is disconnected, brown-out reset kicks in and forces the GPIOs into a high-impedance state. But eventually VDD becomes too low even for this mechanism to work reliably. The GPIOs may then enter an unpredictable state, and some may toggle. The behavior is likely to vary from one GPIO to another, and from one device to the next.

    I cannot see a SW workaround for this. As soon as VDD drops below the BOR threshold, all register writes are forgotten anyway.

    One thing that might help is to speed up the voltage collapse on VDD, e.g. by connecting a bleed device to GND at the same time as the battery is disconnected. More specifically, try to discharge the decoupling capacitor on VDD before DEC1 falls below ~0.5V (DEC1 is the digital core supply)."


    Cheers,
    Håkon. 

  • Hi Håkon,

    Thanks for the update!  

    Here's the scope capture:

    VDD is blue, P0.12 is red.

    The following code is executed before turning off VDD to set the pin back to input / disconnected:

        uint32_t pin_number = 12;
    
        NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
    
        reg->PIN_CNF[pin_number] = 0x2;

    The end result is we need the pin to stay high through the shutdown.  There is a ~50K internal pull-up in the only other device on this signal.

    Cheers,

    Bob

  • That will breach the maximum operating conditions for GPIO voltage of VDD +0.3V and cause the ESD diodes to conduct current, possibly permanently damaging the pin and other circuits in the SoC.

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