Hi,
I wonder if all Tracedata[n] pins are needed for debug? That would make five IO:s useless for other functions. Or is it possible to use 1-bit mode or something similar? If that is possible, are there any limitations other than data speed?
Hi,
I wonder if all Tracedata[n] pins are needed for debug? That would make five IO:s useless for other functions. Or is it possible to use 1-bit mode or something similar? If that is possible, are there any limitations other than data speed?
Found this entry at Segger Forum as per 24'th august 2018. Seems data tracing not yet supported in J-Trace but may be in the pipe. As the 52840 contains a DWT unit, I guess it's capable of producing CPU memory access traces. Is this correct?
Sorry for the late reply. Segger confirmed that the ETM can not do memory tracing, only instruction trace.
The DWT sounds more promising, but the documentation is a bit unclear regarding it's capabilities. You can count the number of accesses to a certain memory address, but I am not sure you can also trace the data content as it is changed. I will have to confirm this with Segger also.
Hi again
According to Segger the DWT can periodically sample certain memory locations, but apparently the solution is not very flexible. They needed some more time to figure out what the sampling period is, and whether or not this can be connected to the trace.
Best regards
Torbjørn