With PPI does the channel interrupt need to be disabled in addition to disabling the peripheral?

[tommy.lane]

Working with SDK 15.0.0

I am porting code from a much older version of the SDK and as such am having to make significant changes to the way the code functions. The previous programmer of the system decided to use a "rolling" read of the ADC values (enabled on channel at a time and rotated through them) then go to sleep until the next system tick.

With the changes in the newer SDK I have the ability to use PPI to trigger the ADC read on a hardware timer without the need to call any timer handler. However, this presents a challenge as the old code was designed to run as low power as possible and still have high frequency ADC updates.

The question comes down to: If I disable the SAADC peripheral and leave the PPI channel connected what would happen? 

Would the PPI not trigger, or would the ADC being off cause a system ASSERT?

Assuming the ADC wouldn't assert ff PPI is enabled and the ADC is disabled. would easy DMA be off and thus reduce the current consumption?

If I want to disable the ADC would the PPI channel stay intact even if the timer and the peripheral were disabled?

[haakonsh]

"Would the PPI not trigger, or would the ADC being off cause a system ASSERT?"

I believe the PPI will attempt to trigger the task as normal, but the SAADC is not enabled and therefore not monitoring its task registers. I doubt an ASSERT will happen as the CPU is not involved in the operation. I believe nothing will happen. 

"Assuming the ADC wouldn't assert ff PPI is enabled and the ADC is disabled. would easy DMA be off and thus reduce the current consumption?"
The EasyDMA is off when the SAADC is disabled. 

"If I want to disable the ADC would the PPI channel stay intact even if the timer and the peripheral were disabled?"
Yes, I believe so. The PPI only operates on registers in RAM and not directly with the peripherals, and as RAM is always available to the PPI system it will stay operational.