Definition of INTENSET/CLR for TIMER

Question

Where to find definition for INTENSET/CLR for TIMERs in 'nRF51_Reference_manual v1.1'? I think I've read it all by now, but still can't find it.
After some digging I found it in the 'nrf51_bitfields.h', but it would somehow be nice to read it in Reference Manual as well.

Ole Morten · Accepted Answer

A decision was made to not document the INTEN registers explicitly for any peripheral, since they are all very similar. The feature of each of them is to choose which events in the peripheral will trigger this peripheral's interrupt. Instead of doing this again and again, this is generally described in section 9.1.6 in the Reference Manual. 
 The corresponding -SET and -CLR registers is a pattern used to avoid read-modify-write cycles. The feature is explained in section 9.1.2 in the Reference Manual. 
 As for a detailed explanation of the INTEN register for the TIMERs, the defines in nrf51_bitfields.h is probably the best. However, once you understand the general pattern, I hope you won't feel the need for an explicit description. The most important point is that with the INTEN register, which is accessed with the set-and-clear-pattern (i.e. through INTENSET and INTENCLR), you can enable and disable each peripheral event's ability to trigger the peripheral's interrupt.