NVMC timing

[michael.crapse]

I'm currently designing a system that requires Nonvolatile memory. Whilst I can accept the 43uS delay to write a word to flash memory. My concern is that it is entirely possible in the operation of the device to erase a flash page. This will take 21ms.

How does this affect the operation of the Soft Device (nominally s130). What concerns should I have with timing? I'm assuming I would have to use the soft device scheduler to ensure the flash erase doesn't coincide with the radio. What precautions should I take as I program the firmware for this operation.

I'm assuming the nonvolatile and the active operation of the Soft Device is incompatible.

Setup: nrf51822 SDK 6.1 S130

[Nguyen Hoan Hoang]

To my knowledge, Pstorage is non blocking. Flash write is hardware. The software only issues the command and then poll it status for completion or wait for completion interrupt (depends if interrupt is implemented or not). It should not affect any time critical path.

[michael.crapse]

According to the nrf51_Series_Reference_Manual_v2.1.pdf on page 14, under section 5.1.5. "The time it takes to erase a page is specified by tPAGEERASE in the product specification. The CPU is halted while the NVMC performs the erase operation."

Looking in the product specification it shows 21ms for a page erase. My understanding of the Softdevice would be that this complete and utter blocking of the CPU would be unacceptable in the central role.

[Nguyen Hoan Hoang]

Thanks for the info. I could understand the CPU halt for erase all but for page why would it halt to CPU. Even CPU halt, your I/O still work and so the radio. I have used it in an acquisition system with 20 i/o begin monitor and operate at the same time as transmitting data over ble. We had issue with, just do not use GPIOTE. I found that GPIOTE latency was to high. It didn't work in our system. We use direct pin change interrupt for that.