My environment: DK 10040, nRF52832, SD 6.1.1, SDK 15.2, SES 3.52
When does the SAADC use power? And when does it stop using power?
I searched the 52832 specification and DevZone but could not find a clear explanation. My best guess is that power consumption begins when the START task is triggered and it will continue to draw power until the buffer is filled and the END event occurs. Is this correct? I found a couple posts that suggest you need to issue the STOP command and disable the SAADC but I do not see this happening in the driver even when low power is enabled.
My guess is based on the low power mode in the driver (nrfx_saadc) which seems to follow this sequence:
- Configure saadc and channels
- Enable saadc
- Start a timer
- Timer expires and triggers START task
- SAADC IRQ receives STARTED event and triggers SAMPLE task
- SAADC IRQ receives END event
- Data is ready for use
- Timer repeats this loop...
Assuming this is correct, I wonder if we can eliminate the CPU interrupt for the STARTED event and instead use the PPI to trigger the SAMPLE task when the STARTED event occurs. This approach would eliminate one CPU interrupt and it would make the timing of the SAMPLE task more deterministic. The new sequence would be:
- Configure saadc and channels
- Enable saadc
- Start a timer
- Timer expires
- PPI triggers START task
- SAADC sends the STARTED event
- PPI triggers the SAMPLE task
- SAADC sends the END event
- IRQ handles the END event
- Timer repeats this loop...
I coded this up and it seems to work fine. I plan to measure power as soon as I get the required tools. Do you see any concerns with this approach? Are there other ways to save power?
Currently I use a timer with frequency 31250Hz. Would I save a lot of power if I use RTC instead? Thanks!
