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[NRF51] UART lock up at 921600 bps

Hi,

We have an issue with app_uart_fifo which occasionally locks up during data transfer from NRF51 to an other uC.

System description:

We're using first revision chip (QFAAC0) and the UART don't use hardware flow control (PCB is ready without CTS & RTS connected).

We have transmission from other uC to NRF51 (around 60 B/s), which causes missing bytes problem. That's why we've decided to increase baud rate to the highest possible rate in order to lower down missing bytes within each packet. We still have corrupted packets but number of these much less than for 115200 bps which we've used before.

Problem description: Unfortunately, as soon as we've increased baud rate to 921600, very rare lock ups have started to occur. It seems that the lock up occurs more often when more data is transfered from NRF51, e.g. when we transfer around 4500 B/s issue occurs around every 40 minutes and for around 600 B/s lock up occurs roughly every 5 hours period.

I've been testing the same source code with 460800 bps and everyting seems to be working fine (14 hours test).

The source locks up in the fputc function:

int fputc(int ch, FILE * p_file) 
{
    while(app_uart_put((uint8_t)ch) != NRF_SUCCESS)
        ;
    return ch;
}

The tx fifo is full so the function locks up as it's not possible to add any byte to the fifo and int the same time the transmission interrupt doesn't occur. The debugger doesn't break in the following source code:

    // Handle transmission.
if (NRF_UART0->EVENTS_TXDRDY != 0)
{
    // Clear UART TX event flag.
    NRF_UART0->EVENTS_TXDRDY = 0;
    on_uart_event(ON_TX_READY);
}

Do you have any hint what could cause such issue, please? Let me know if I could provide some more information from the debugger which can help with investigation.

Kind Regards, Krzysztof Rosinski

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  • Hi Asbjørn,

    Thank you for quick reply.

    We've replaced chip to QFAAG0 and I'm now going to run long term test at 921600 bps (still without hardware flow control) though.

    Regarding the first revision chips, I understand that these have only 2 bytes buffers but I'd thought that a byte should be simply overwritten in that buffer so transmission is corrupted (and this happens quite frequently). I don't understand however how it is possible that the the fifo fails completely and that it fails only for the transmission from NRF51 chip. The reception interrupts still occurs even though the code locks up in the fputc function.

    Can you give me any hint regarding this, please?

    Update 18/10/14:

    I've caught the lock up in the debugger, this is what have so far:

    • m_current_state is set to UART_ON however the EVENTS_TXDRDY interrupt doesn't occur, due to that state doesn't change to UART_READY, the software fifo fills up and lock up occurs.
    • NRF_UART0->TASKS_STARTTX = 0
    • NRF_UART0->TASKS_STOPTX = 0

    Many thanks, Krzysztof Rosinski

Reply
  • Hi Asbjørn,

    Thank you for quick reply.

    We've replaced chip to QFAAG0 and I'm now going to run long term test at 921600 bps (still without hardware flow control) though.

    Regarding the first revision chips, I understand that these have only 2 bytes buffers but I'd thought that a byte should be simply overwritten in that buffer so transmission is corrupted (and this happens quite frequently). I don't understand however how it is possible that the the fifo fails completely and that it fails only for the transmission from NRF51 chip. The reception interrupts still occurs even though the code locks up in the fputc function.

    Can you give me any hint regarding this, please?

    Update 18/10/14:

    I've caught the lock up in the debugger, this is what have so far:

    • m_current_state is set to UART_ON however the EVENTS_TXDRDY interrupt doesn't occur, due to that state doesn't change to UART_READY, the software fifo fills up and lock up occurs.
    • NRF_UART0->TASKS_STARTTX = 0
    • NRF_UART0->TASKS_STOPTX = 0

    Many thanks, Krzysztof Rosinski

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