Hi Guys,
I facing issue on one of my project, our HW require 2 set of TWI and one QSPI/SPI. I notice SPI0/1 cannot be used because I need both TWI0 and TWI1 to be supported. Please advice me how can I have all QSPI/SPI + TWI0 and TWI1
Hi Guys,
I facing issue on one of my project, our HW require 2 set of TWI and one QSPI/SPI. I notice SPI0/1 cannot be used because I need both TWI0 and TWI1 to be supported. Please advice me how can I have all QSPI/SPI + TWI0 and TWI1
Hi,
Peripherals with the same ID cannot be used simultaneously. As you can see from the Instantiation table, QSPI does not overlap with any other peripherals (ID 41). The TWI and normal SPI peripherals share ID 3 and 4, but there is also a TWIM peripheral with ID 35, so you can configure what you want without any overlap.
(If there had to be overlap, which does not seem to be the case here, you could instead disable one peripheral before you switch to the other. You could also consider using less peripheral, for instance you often only need one TWIM peripheral, as TWI is a bus where multiple slaves could be connected to a single master. The same applies to SPI, where you typically use a chip select signal to select which slave to talk to.)
Hi,
Peripherals with the same ID cannot be used simultaneously. As you can see from the Instantiation table, QSPI does not overlap with any other peripherals (ID 41). The TWI and normal SPI peripherals share ID 3 and 4, but there is also a TWIM peripheral with ID 35, so you can configure what you want without any overlap.
(If there had to be overlap, which does not seem to be the case here, you could instead disable one peripheral before you switch to the other. You could also consider using less peripheral, for instance you often only need one TWIM peripheral, as TWI is a bus where multiple slaves could be connected to a single master. The same applies to SPI, where you typically use a chip select signal to select which slave to talk to.)
Thanks. I notice there is SPI ID 3 available in the table. I could use that for SPI.