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nRF51822 power consumption when BLE advertising/connected

Eliot Stock

We're trying to decide at what voltage we should run our nRF51822 on the next revision of our board. To date we've been doing fine at 1.8V. The current drawn on a 3.7V lithium ion battery while in a connected state for BLE is 0.8mA at the moment.

All other things being equal, we would now prefer to run the Nordic at 3.0V because we have other modules on the board running at 3.0V and we want to use the UART with them without doing any level shifting on the UART lines.

My question is: by raising the voltage at which we're running the Nordic, are we also raising the power consumption when in a BLE connected state? Or is the power consumption constant so by raising the voltage we're lowering the current drawn to arrive at the same power consumption?

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  • 0

    Hi Eliot

    The current consumption is independent of the supply voltage. However, if you increase the supply voltage, the power consumption will increase as the current is constant. There are two internal regulators, one gives 1.7V output for the analog parts, one gives 1.2V output for the digital parts. The energy for lowering the voltage from your supply voltage down to the 1.7V or 1.2V is burned up in order to obtain the correct input voltage for the peripherals on the chip. However, when using DCDC, it will lower supply voltages >2.1V down to 1.9V and conserve much of the energy that would otherwise be wasted in order to lower the voltage. The difference between the DCDC and regulator is the following:

    • Regulator will lower voltage, the input current and output current is the same
    • DCDC will lower voltage, the input current is lower than the output current.

    So the DCDC will use much of the energy obtained by lowering the voltage to actually increase the current. The drawback of DCDC is however that it will itself also consume current just to have it operational. So the tradeoff is to have DCDC only enabled at the moments the nRF51 is drawing high current, then disable it when the chip is using low current. An explanatory sketch of how the DCDC works vs LDO is shown here.

    The current recommendation for use of the DCDC are however described on this thread.

    Update 29.10.2014 The voltage levels on the GPIO are independent of the DCDC. If the supply voltage for the nRF51 is 3.0V then the GPIO output voltage will be 3.0V, no matter if the DCDC is enabled or not.

    Yes, you waste more energy if the supply voltage is 2.4V instead of 1.8V, both when using DCDC and LDO, even though when using DCDC it will potentially waste less energy. Some customers have used external DCDC to lower battery voltage down to 1.8V, and thereby saving current. DCDC is more efficient the higher the battery voltage. A DCDC is not that efficient when supply voltage is 2.1V-2.5V, more or less on par with LDO (regulator), as the DCDC itself draws current when enabled, but potentially much better when supply voltage is >3.0V.

    If the voltage level on the UART of the peer device is 3.0V, then the voltage level of the nRF51 should not be less than 3.0V without level shifters. If the voltage of the nRF51 is lower than 2.7V (the absolute limit), ESD protection diodes on the GPIO pins will short current to ground, causing your system to draw excessive current. Allowed voltage level on GPIO pins is documented in nRF51822 PS v2.0, table 16. More specifically the ESD diodes will start to leak current when the supply voltage goes below 3.0V and will short excessive current when the supply voltage reaches 2.7V.

    It is however safe to have the supply voltage for the nRR51 a little higher than the UART peer voltage, as the nRF51 will detect logical high level above VDD*0.7, as statet in nRF51822 PS v2.0, table 56.

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  • 0

    Hi Eliot

    The current consumption is independent of the supply voltage. However, if you increase the supply voltage, the power consumption will increase as the current is constant. There are two internal regulators, one gives 1.7V output for the analog parts, one gives 1.2V output for the digital parts. The energy for lowering the voltage from your supply voltage down to the 1.7V or 1.2V is burned up in order to obtain the correct input voltage for the peripherals on the chip. However, when using DCDC, it will lower supply voltages >2.1V down to 1.9V and conserve much of the energy that would otherwise be wasted in order to lower the voltage. The difference between the DCDC and regulator is the following:

    • Regulator will lower voltage, the input current and output current is the same
    • DCDC will lower voltage, the input current is lower than the output current.

    So the DCDC will use much of the energy obtained by lowering the voltage to actually increase the current. The drawback of DCDC is however that it will itself also consume current just to have it operational. So the tradeoff is to have DCDC only enabled at the moments the nRF51 is drawing high current, then disable it when the chip is using low current. An explanatory sketch of how the DCDC works vs LDO is shown here.

    The current recommendation for use of the DCDC are however described on this thread.

    Update 29.10.2014 The voltage levels on the GPIO are independent of the DCDC. If the supply voltage for the nRF51 is 3.0V then the GPIO output voltage will be 3.0V, no matter if the DCDC is enabled or not.

    Yes, you waste more energy if the supply voltage is 2.4V instead of 1.8V, both when using DCDC and LDO, even though when using DCDC it will potentially waste less energy. Some customers have used external DCDC to lower battery voltage down to 1.8V, and thereby saving current. DCDC is more efficient the higher the battery voltage. A DCDC is not that efficient when supply voltage is 2.1V-2.5V, more or less on par with LDO (regulator), as the DCDC itself draws current when enabled, but potentially much better when supply voltage is >3.0V.

    If the voltage level on the UART of the peer device is 3.0V, then the voltage level of the nRF51 should not be less than 3.0V without level shifters. If the voltage of the nRF51 is lower than 2.7V (the absolute limit), ESD protection diodes on the GPIO pins will short current to ground, causing your system to draw excessive current. Allowed voltage level on GPIO pins is documented in nRF51822 PS v2.0, table 16. More specifically the ESD diodes will start to leak current when the supply voltage goes below 3.0V and will short excessive current when the supply voltage reaches 2.7V.

    It is however safe to have the supply voltage for the nRR51 a little higher than the UART peer voltage, as the nRF51 will detect logical high level above VDD*0.7, as statet in nRF51822 PS v2.0, table 56.

Children
  • 0 in reply to Stefan Birnir Sverrisson

    OK, thanks. So the DCDC is out of the question for us on this version of our boards because we have your second revision hardware and we're using the Soft Device. But the real question is, if we want to avoid adding level shifters to the UART lines and the other end of those UART lines are running at 3.0V, meaning logic high on those lines needs to be 70 to 80% of that (2.1V to 2.4V), is it a bad idea to run the Nordic at 2.4V and not use the DCDC? And you're saying, yes, it's wasteful to do that because when using the regulator, the current will still be 0.8mA but this time at 2.4V instead of 1.8V, so higher power. Have I got that right?

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