I have found the following piece of code on an example from a Nordic employee. I'm curious as to its purpose.
NRF_TIMER0->EVENTS_COMPARE = 0;
Why is the register set, and then read just after?
I think a good answer can be found here:
"The memory barrier instructions, DMB and DSB, can be used to ensure that the write buffer on the processor has completed its operation before subsequent operations can be started. However, it does not check the status of the bus level write buffers. In such cases, if the system is based on AHB or AHB Lite, you might need to perform a dummy read through the bus bridge to ensure that the bus bridge has completed its operation. Alternatively, a SoC design might have a device specific status register to indicate whether the bus system write buffer is idle."
In short, register accesses take place over a peripheral bus, and sometimes the writes are buffered (the idea being to batch a bunch of writes into a burst if you can). But sometimes you need to be sure a register write actually completes before you proceed further through your program, and forcing a read access does this.
You're basically defeating a performance optimization in order to achieve correct program behavior. This is a common pastime in embedded and systems programming. :)
From the nRF52832 Product Specification v1.4Section 15.8.1 Peripheral Interface, Interrupt clearing
When clearing an interrupt by writing "0" to an event register, or disabling an interrupt using the INTENCLR register, it can take up to four CPU clock cycles to take effect.
So, while I like your answer, and am still thinking about whether your answer is in fact the underlying reason for requiring clearing, I think the answer is not a pipeline flush but merely a implementation of how Nordic's registers work.