What is the power and clock model of peripheral in NRF51?

Question

Hello, 
 I was puzzled by RM. 
 I notice POWER control register in peripheral(UART,SPI,TWI) module. 
 Please answer following questions about the relation between system power and the peripheral power register value. 
 
 Will UART be powered when system power off and uart register power on? 
 Will UART be powered when system power on (constant latency) and UART register power off? 
 Will UART be powered when system power on (low power) and UART register power off? 
 
 ==================================================== 
 Will system control logic shutdow power of modules when system in power on (low power) mode? 
 Alternatively, you can answer next question. 
 Is there any possible that UART be power off by control logic, when system power on (low power) and UART register power on? 
 If yes, can registers retention their values? 
 ===================================================== 
 What does IDLE and RUN mean in RM/PS, is it something about clock gating? 
 Is IDLE the only low power mode of model? 
 If yes: 
 
 Will module clock be automatically gated in IDLE mode? 
 How does control logic knows module in IDLE mode? 
 Can clock automatically on when needed, eg. new byte comes in UART? 
 Is this schematic transparent to software? 
 
 =================================================== 
 What is the relationship between ENABLE and IDLE state? 
 Is it possible for a module to enter IDLE when ENABLE is true? 
 For UART, 
 
 Will it be IDLE when not enabled? 
 Will it be RUN once enabled? 
 Will it be IDLE when not transmitting and not receiving? 
 Will it be RUN only when transmitting or receiving? 
 
 Thanks a lot! 
 Edit: format, tags.

Ole Morten · Accepted Answer

For information on the low frequency clock model (32kHz), look at this thread . 
 For information on the high frequency clock model (16MHz), look at this thread . 
 With the nRF51822, there is just two power modes you need to be aware off, system on idle and system off. 
 System on, idle 
In this mode, all peripherals that are enabled when entering sleep stays enabled, and you can wake up on any interrupt. All clocks and regulators that are not required by a running peripheral will be turned off, but all RAM and registers are retained. When the chip comes out of sleep, it continues where it left off. 
 With the softdevices, you can enter this sleep mode using sd_app_event_wait(), and if you don't use the softdevice, you can use __WFE(). sd_app_event_wait() function (inside power_manage() function) is used in most of the examples in the nRF51 SDK. An example on how to use __WFE() is given in the system-on-wakeup-on-gpio example on Nordic's Github . 
 The base current consumption in this mode is given in table 32 in the nRF51822 PS v3.1 as I_ON, 2.6 µA. The current consumption of any running peripheral, and their required clocks and regulators will come on top of this. The block requirements of the different peripherals can be seen in table 33 in section 8.3 in the nRF51822 PS v3.1 . 
 Sub-power modes 
There are also two sub-power modes, the default LOWPWR, and CONSTLAT. These are described in section 11.1.4 in the nRF51 Reference Manual . Using the CONSTLAT mode will keep the 16 MHz clock running all the time, so that the wake-up time is constant and low (< 3 µs). This comes with the cost of having the 16 MHz clock always running, even when no peripherals need it, which gives a consumption increase of several hundred µA. The default is to use LOWPWR. 
 System off 
In this mode, all peripherals, clocks and regulators are turned off, and the only wake-up sources are a reset and GPIOs with SENSE configured (SENSE field in PIN_CNF set to low or high). By default, all RAM is also turned off, but this can optionally be kept on by changing the RAMON register. When the chip comes out of this sleep mode, it always starts from reset, and RAM (if not configured otherwise) and registers that are not marked as retained are cleared. See table in section 11.1.7.8 in the nRF51 Reference Manual for details on reset behavior. 
 With the softdevices, you can enter this mode with sd_power_system_off(), and without them, by writing 1 to the SYSTEMOFF register in the POWER peripheral. When entering system off, all peripherals are automatically turned off, so no preparation is needed. 
 The base current consumption in System Off is given in table 32 in the nRF51822 PS as I_OFF, 0.6 µA. RAM retention increases this, as stated in the same table. Since all peripherals and clocks are turned off, which peripherals are enabled when entering this mode doesn't matter for the current consumption. 
 General considerations 
All peripherals are per default off, and only peripherals that have been explicitly enabled will be on at any time. To achieve low current consumption with the nRF51, the general recommendation is therefore to only turn perpiherals on for as short time as possible, and explicitly turn them off whenever they are not needed. This is usually done by writing a Disabled value to the peripheral's ENABLE register, and will ensure that they don't keep the clock running when it isn't actually needed. 
 In addition, it's always safe to enter system on, idle, from the main context, since whatever has been enabled before you enter this mode will stay enabled through it. This is therefore very well suited to be the only action in the main loop, and you should make all other actions in your application depend on interrupts or events coming either from perpiherals (timers) or from the BLE/ANT stacks. 
 Use system off only when you can live with requiring user action (i.e. button presses) to wake you up again, and with a reset being done (i.e. when you don't have any state information that you need to preserve). 
 Finally, when doing current measurements, remember that the debug interface of the nRF51 consumes > 1 mA, so do a power-on-reset after flashing. See this question for details. 
 Edit: Some clarifications.

What is the power and clock model of peripheral in NRF51?

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