Vias dimension for CSP nRF51822 4 layer pcb

Question

Hello 
 for a 4 layer design with the nRF51822, how is it best to choose the layers? In the datasheet of the balun (bal_nrf02D3) there is a hint, I guess it is more or less just ground planes..? (1:Signal, 2:signal and polygon GND, 3:GND expect chip area, 4:GND) ? Would it be locking for trouble if I choose one layer as a power layer? I would like to do: Signal:some_signal_and_gnd:power:gnd(inkl.battery) 
 Would it be possible to reach the 4th layer with one via straight (under the chip, using csp)? (Dimensions as in the balun-datasheet: 230:930:230 um)
In the balun-datasheet the vias under the csp are just reaching the very next layer under the chip, is this the maximum length for these kind of vias probably? (Expect the one bigger via reaches the GND layer.) 
 how about the (pcb-)antenna area, keep all layers out of that area I guess? 
 many thanks in advance

Asbjørn · Accepted Answer

You can mix around with the layer stack up. You should avoid running power plane or traces directly under the balun and the part from VDD_PA, ANt1 and ANT2 pins towards the antenna. There should only be ground under that part. There's no problem with running the vias deeper, but it might be changing the requirement for the processing of the board. 
 Antenna should be places in an open as possible area. Please have a look at some of our kits if you're not familiar and follow the reference layout and schematic closely. The antenna would normally be placed in a corner or at the end to make sure it in as close to free air as possible.