Do flash operations block DMA activity?

[droberson]

Hardware:

nRF52840 DK

S140 Soft Device

SDK 15.2.0

Hello,

I want to confirm my understanding of the impact of flash operations on the nRF5240 when using the SoftDevice and DMA.

Flash writes and erases block the CPU as defined in the product spec and SotDevice datasheets. My question is, do flash operations also block DMA operation? For example, say I want to write 256 bytes of data to flash while receiving data from a SPI device via DMA into a RAM buffer. I understand that my DMA interrupts may be delayed until the flash operation completes, but can both operations occur simultaneously? I would assume so, but I want to make 100% sure.

Thanks!

Derek

[Jared]

Hi,

Yes, this shouldn't be a problem as long as the SPI Master doesn't access the same slave as the CPU is accessing. If they did, the CPU would get the highest priority. 

Best regards

Jared 

[droberson]

Jey Jared,

By "slave" in this case do you mean one of the 9 AHB RAM slaves? In other words, as long as the SPIM DMA module isn't writing to the same chunk of RAM that the CPU is accessing?

Thanks,

Derek

[Jared]

That is correct!

[Kevin Bernard]

Hi,

This old thread is exactly the question I am wondering about but there is something I do not understand with the answer.

Since the CPU is stalled during flash write and erase, the CPU is not accessing any AHB slave during that time, right ? therefore I do not understand the answer to the original question.

In my project, I'm using the UARTE peripheral (with DMA) and I would like to know if during flash write/erase the UART DMA will work correctly in reception or transmission.

Best regards,

Kevin