SWD causing undesirable reset

[Charles Manning]

Hello

I have an nRF51822 serving as s supervisory micro for an embedded Linux board. Two GPIO pins from the main CPU are hooked up to the nRF51822 to implement SWD for the purpose of upgrading the nRF.

I have written all the SWD code and the upgrade mechanism works fine, all except for one thing....

Occasionally, maybe one of of 10 times, the DIF does not appear to switch out of normal mode and the nRF seems to see the first changes on the SWDIO line as a reset.

The reason I believe their is a reset happing is that one of the GPIO pins I am monitoring changes from output to input.

I send a preample of:

• Drive SWDIO line high. (it is already high anyway).
• Send 150 strobes on SWDCLK, ending with SWDCLK high. Since this is driven by software, the frequency is 1.7MHz, but there are some stalls.
• Send JTAG->SWD magic code. This is what occasionally triggers the reset.
• Send 150 more 1 bits. ...

Even though the JTAG to SWD code triggers a reset, the device still enters debug mode and access to the internal debug is fine. It appears that the DIF is passing though the SWD signals, yet it still triggering a reset.

Are there any subtleties to getting the DIF to correctly leave Normal mode?

[Asbjørn]

The first time you enter DIF a change to SWDIO line causes a reset due to the multiplexing with the nRESET functionality. So first time you enter DIF you should expect this. After that you will have to enable the reset functionality again from the RESET register.

[Roger Clark]

I'm seeing a similar problem all the time.

When I have the Black Magic Probe (SWD programmer connected), it drives both SDIO and SWCK low in its initialisation sequence, however it appears that driving SDIO low causes my nRF51 to immediately reset and also Halt its operation.

If I disconnect the SDIO line from the programmer and manually pull it low, it also resets and halts the processor.

The work-around appears to initially drive SDIO high, as the evaluation board I'm using does not pull this pin high or low (i.e its floating) www.waveshare.com/.../Core51822-Schematic.pdf

However from what I have read, I thought that both SDIO and SWCK are supposed to be pulled low - or perhaps its just SCK that is supposed to be pulled low (as this is the configuration on my evaluation board)