SAADC Offset Calibration errors and input resistance

[while(1)]

nrf52832.

SDK14.2

Segger ES V3.34a

With an initial prototype batch of 30, we have noticed 4 modules that have incorrect voltage readings, reading low ("Bad Modules").

Normally we implement the calibration routine for the offset, but found when we disabled this routine the 4 low reading parts improved in performance, but still had errors.  This lead to debugging and capturing the ADC readings with/without the calibration routine enabled and comparing bad modules with good modules.

We noted the ADC Counts from three of the ADC pins  An0, An1, An2

On the bad module we noticed the following.

The calibration offset was made worse by ~300 steps after calibration.

The input impedance w.r.t 0V for Ain0 was lower on a bad module which affected the potential divider reading.

 Ain2 s/c to 0V had a greater negative offset to start with compared with a good module, (prior to calibration)

Settings on both modules

//set configuration for saadc channel 0
channel_0_config.resistor_p = NRF_SAADC_RESISTOR_DISABLED;
channel_0_config.resistor_n = NRF_SAADC_RESISTOR_DISABLED;
channel_0_config.gain = NRF_SAADC_GAIN1_5;
channel_0_config.reference = NRF_SAADC_REFERENCE_INTERNAL;
channel_0_config.acq_time = NRF_SAADC_ACQTIME_3US;

channel_0_config.mode = NRF_SAADC_MODE_SINGLE_ENDED;
channel_0_config.pin_p = (nrf_saadc_input_t)(NRF_SAADC_INPUT_AIN0);
channel_0_config.pin_n = NRF_SAADC_INPUT_DISABLED;


//set configuration for saadc channel 1
channel_1_config.resistor_p = NRF_SAADC_RESISTOR_DISABLED;
channel_1_config.resistor_n = NRF_SAADC_RESISTOR_DISABLED;
channel_1_config.gain = NRF_SAADC_GAIN1_5;
channel_1_config.reference = NRF_SAADC_REFERENCE_INTERNAL;
channel_1_config.acq_time = NRF_SAADC_ACQTIME_3US;
channel_1_config.mode = NRF_SAADC_MODE_SINGLE_ENDED;
channel_1_config.pin_p = (nrf_saadc_input_t)(NRF_SAADC_INPUT_AIN1);
channel_1_config.pin_n = NRF_SAADC_INPUT_DISABLED;

//set configuration for saadc channel 2
channel_2_config.resistor_p = NRF_SAADC_RESISTOR_DISABLED;
channel_2_config.resistor_n = NRF_SAADC_RESISTOR_DISABLED;
channel_2_config.gain = NRF_SAADC_GAIN1_5;
channel_2_config.reference = NRF_SAADC_REFERENCE_INTERNAL;
channel_2_config.acq_time = NRF_SAADC_ACQTIME_3US;
channel_2_config.mode = NRF_SAADC_MODE_SINGLE_ENDED;
channel_2_config.pin_p = (nrf_saadc_input_t)(NRF_SAADC_INPUT_AIN2);
channel_2_config.pin_n = NRF_SAADC_INPUT_DISABLED;

//Configure SAADC

/saadc_config.low_power_mode = False; //Disable low power mode.
saadc_config.resolution = NRF_SAADC_RESOLUTION_14BIT; //Set SAADC resolution to 14-bit.
saadc_config.oversample = NRF_SAADC_OVERSAMPLE_32X; //Set oversample to 32x. 

We are using 0.1% resisters for the p.d.

Ain0 - p.d with 82.5K and 7.5K

Ain1 - LM61

An2 - 100K pull down to 0V

Results

Applied voltage constant to Ain0 and Ain1  'with and without' calibration for comparison

Bad module -

Ain                        No CAL                                          WITH  CAL                       DIFF

0                            5857                                                   5532                            -325     

1                            4714                                                   4438                            -276

2                            -20                                                       -330                            -310

Good module - 

Ain                       No CAL                                          WITH  CAL                       DIFF

0                            5699                                                 5704                              5  

1                            4830                                                 4836                              6

2                            -8                                                       -2                                  7

Are there any chip revisions that could cause such a loading of the A/D input and also cause the calibration routine to make things worse.

What is done internally to carry out the calibration routine?

Any help suggestions or thoughts?

[hmolesworth]

As a test you might try slowing down the sampling (say to 10uSec) just in case those parts have higher external impedance for some reason, maybe component tolerance or even incorrect components in the case of resistors or damaged if there are any aliasing filter capacitors. The calibration is ineffective if the sampling time doesn't allow full 12-bit settle on the internal sampling capacitor.

TACQ [μs]    Max source resistance [kOhm]
      3               10
      5               40
      10             100
      15             200
      20             400
      40             800

[while(1)]

Hi hmolesworth,

Thanks for taking your time to look at this. I have the same results with 40uS with no change or improvements. We have also swapped all the external components from one board to the other. My issue here is two distinct difference in operation from one device to another, both with the same firmware and operating conditions. It's my hunch that what ever is loading our external p.d. is also affecting the calibration. 

[hmolesworth]

There are some errata issues when Tacq < 5uSecs, so 40uSec test rules out those. This is another errata, easy to check, which might vary between specific dies of the same code:

3.24 [86] SAADC: Triggering START task after offset calibration may write a sample to RAM

Also this one, but only for Tacq > 10uSecs

3.50 [178] SAADC: END event firing too early

Are the dies all the same code (die rev & date)? Looks like a question for Nordic team ..

[while(1)]

The dies are all  nRF5283-QFAA-E00.