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softdevice making use of extra sram in rev 3 QFAC silicon?

I have recently started using the new rev 3 parts with 32K of SRAM and I was wondering what the timeframe is for the softdevice to take advantage of the extra memory?

My application transmits very little but periodically receives 40-50KB of data, so most of the extra SRAM will be used as working buffers and will make life my life much easier. However, I'm willing to give up some of the SRAM if the softdevice could:

  • support larger MTU size and fragmentation/reassembly
  • reliably receive more packets per interval
  • more memory for service configuration data (NRF_ERROR_NO_MEM)

Are these features on the horizon?

With the 16K code, I can't provide all the characteristic data I would like because I get NRF_ERROR_NO_MEM when adding characteristics, I was hoping that some of the extra SRAM could be used for this data.

I suspect the answer will just be consult our regional sales manager, but I thought I'd ask.

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  • Currently on the S110 v7.1.0 this is fixed and you can use the full RAM. I suspect that you might be using the S120 and it will of course be fixed/opened on this as well to enable customers to utilize the full RAM.

    I don't want to make predictions for future plans here, so yes, you would have to contact our regional sales manager to get more information on this. If you don't know who that is, let me know where you are located and I'll patch you through.

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  • Currently on the S110 v7.1.0 this is fixed and you can use the full RAM. I suspect that you might be using the S120 and it will of course be fixed/opened on this as well to enable customers to utilize the full RAM.

    I don't want to make predictions for future plans here, so yes, you would have to contact our regional sales manager to get more information on this. If you don't know who that is, let me know where you are located and I'll patch you through.

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