QSPI not clearing "BUSY"

[Adam Gerken]

I'm trying to use the QSPI periph to interface to a Flash, the project is based on the blinky and has UART and SAADC added in so far. I can use nrfx_qspi_cinstr_xfer to read registers just fine, but when I try to write or read to the Flash, I can't seem to get the "busy" flag to clear. I'm using the code straight out of the qspi example, which works fine, but I can't get it to work in my program.

I initialize the qspi and it seems to work fine:

    uint32_t err_code;

    //Init the perif
    nrfx_qspi_config_t config = NRFX_QSPI_DEFAULT_CONFIG;

    err_code = nrfx_qspi_init(&config, qspi_handler, NULL);
    APP_ERROR_CHECK(err_code);

I set up my handler, but it never gets to it:

static void qspi_handler(nrfx_qspi_evt_t event, void * p_context)
{
    UNUSED_PARAMETER(event);
    UNUSED_PARAMETER(p_context);
    m_qspi_finished = true;
    printf("qspi_handler\r\n");
}

I can initialize the flash, no problem, read it's device ID fine. When I write to the qspi, it will write as expected according to the analyzer, return an error of 0, then lock up at the while(!m_qspi_finished); If I remove that, I get error 17, which is BUSY.

    uint8_t err_code;
    static uint8_t m_buffer_tx[2] = {0xBE,0xEF};

    err_code = nrfx_qspi_write(m_buffer_tx, 2, 0);
    printf("err_code: %d\r",err_code);
    while(!m_qspi_finished);
    m_qspi_finished = false;

    nrf_delay_ms(100);

I'm not sure if I've missed a config setting somewhere, I think my sdk_config.h is fine:

// <e> NRFX_QSPI_ENABLED - nrfx_qspi - QSPI peripheral driver
//==========================================================
#ifndef NRFX_QSPI_ENABLED
#define NRFX_QSPI_ENABLED 1
#endif
// <o> NRFX_QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns).  <0-255> 


#ifndef NRFX_QSPI_CONFIG_SCK_DELAY
#define NRFX_QSPI_CONFIG_SCK_DELAY 1
#endif

// <o> NRFX_QSPI_CONFIG_XIP_OFFSET - Address offset in the external memory for Execute in Place operation. 
#ifndef NRFX_QSPI_CONFIG_XIP_OFFSET
#define NRFX_QSPI_CONFIG_XIP_OFFSET 0
#endif

// <o> NRFX_QSPI_CONFIG_READOC  - Number of data lines and opcode used for reading.
 
// <0=> FastRead 
// <1=> Read2O 
// <2=> Read2IO 
// <3=> Read4O 
// <4=> Read4IO 

#ifndef NRFX_QSPI_CONFIG_READOC
#define NRFX_QSPI_CONFIG_READOC 4
#endif

// <o> NRFX_QSPI_CONFIG_WRITEOC  - Number of data lines and opcode used for writing.
 
// <0=> PP 
// <1=> PP2O 
// <2=> PP4O 
// <3=> PP4IO 

#ifndef NRFX_QSPI_CONFIG_WRITEOC
#define NRFX_QSPI_CONFIG_WRITEOC 3
#endif

// <o> NRFX_QSPI_CONFIG_ADDRMODE  - Addressing mode.
 
// <0=> 24bit 
// <1=> 32bit 

#ifndef NRFX_QSPI_CONFIG_ADDRMODE
#define NRFX_QSPI_CONFIG_ADDRMODE 0
#endif

// <o> NRFX_QSPI_CONFIG_MODE  - SPI mode.
 
// <0=> Mode 0 
// <1=> Mode 1 

#ifndef NRFX_QSPI_CONFIG_MODE
#define NRFX_QSPI_CONFIG_MODE 0
#endif

// <o> NRFX_QSPI_CONFIG_FREQUENCY  - Frequency divider.
 
// <0=> 32MHz/1 
// <1=> 32MHz/2 
// <2=> 32MHz/3 
// <3=> 32MHz/4 
// <4=> 32MHz/5 
// <5=> 32MHz/6 
// <6=> 32MHz/7 
// <7=> 32MHz/8 
// <8=> 32MHz/9 
// <9=> 32MHz/10 
// <10=> 32MHz/11 
// <11=> 32MHz/12 
// <12=> 32MHz/13 
// <13=> 32MHz/14 
// <14=> 32MHz/15 
// <15=> 32MHz/16 

#ifndef NRFX_QSPI_CONFIG_FREQUENCY
#define NRFX_QSPI_CONFIG_FREQUENCY 15
#endif

// <s> NRFX_QSPI_PIN_SCK - SCK pin value.
#ifndef NRFX_QSPI_PIN_SCK
#define NRFX_QSPI_PIN_SCK 19
#endif

// <s> NRFX_QSPI_PIN_CSN - CSN pin value.
#ifndef NRFX_QSPI_PIN_CSN
#define NRFX_QSPI_PIN_CSN 17
#endif

// <s> NRFX_QSPI_PIN_IO0 - IO0 pin value.
#ifndef NRFX_QSPI_PIN_IO0
#define NRFX_QSPI_PIN_IO0 20
#endif

// <s> NRFX_QSPI_PIN_IO1 - IO1 pin value.
#ifndef NRFX_QSPI_PIN_IO1
#define NRFX_QSPI_PIN_IO1 21
#endif

// <s> NRFX_QSPI_PIN_IO2 - IO2 pin value.
#ifndef NRFX_QSPI_PIN_IO2
#define NRFX_QSPI_PIN_IO2 22
#endif

// <s> NRFX_QSPI_PIN_IO3 - IO3 pin value.
#ifndef NRFX_QSPI_PIN_IO3
#define NRFX_QSPI_PIN_IO3 23
#endif

// <o> NRFX_QSPI_CONFIG_IRQ_PRIORITY  - Interrupt priority
 
// <0=> 0 (highest) 
// <1=> 1 
// <2=> 2 
// <3=> 3 
// <4=> 4 
// <5=> 5 
// <6=> 6 
// <7=> 7 

#ifndef NRFX_QSPI_CONFIG_IRQ_PRIORITY
#define NRFX_QSPI_CONFIG_IRQ_PRIORITY 6
#endif

// </e>

[Adam Gerken]

Actually, it looks like it just checks the status register and sets the write bit, but never sends any data. Still returns error 0 though:

[Kenneth]

Can it be a interrupt priority issue, for instance that you are trying to call qspi transfer from an interrupt with same priority as the qspi_handler() is pending?

Also make sure to set m_qspi_finished as volatile.

[Adam Gerken]

I initially thought the same thing, but the transfer is being called from my main function right now. The interrupt level is 6, the only others I changed are higher than that. Will this interrupt not trigger if there is a higher one pending or something? I have handlers for all the other ones so I'm not sure what it could be.

I thought this was curious in nrfx_qspi.c around line 148 in nrfx_qspi_init()

/* QSPI interrupt is disabled because the device should be enabled in polling mode (wait for activate
       task event ready)*/
    nrf_qspi_int_disable(NRF_QSPI, NRF_QSPI_INT_READY_MASK);

This line is also in the qspi example, but the qspi_handler works just fine in that example.

[Kenneth]

Adam Gerken said:

Will this interrupt not trigger if there is a higher one pending or something?

Higher level interrupts must finish executing before the lower level interrupt handlers will run yes. Not sure if I have any good suggestion other than either increase the priority of the qspi to see if that changes things and/or disable other modules in your application until you can see a change?

[Adam Gerken]

Yeah, makes sense. Moving the interrupt priority level up each step, up to 0, didn't change anything, neither did removing everything else from my project.

Thanks for trying though.