nRF51 Dongle to Taiyo Yuden EBAGJNZXX eval board

[william-krs]

I have a working/functioning project running on the nRF51 dongle that I want to develop for production. To save a step in FCC certification I am developing on an FCC approved module from Taiyo Yuden, EBAGJNZXX.

The dongle has a 16MHz crystal and the TY board has a 32MHz crystal.

I have changed:

system_nrf51.c

#define __SYSTEM_CLOCK      (32000000UL)     /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */
//#define __SYSTEM_CLOCK      (16000000UL)     /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */

skd_congif.h

#if  CLOCK_ENABLED
// <o> CLOCK_CONFIG_XTAL_FREQ  - HF XTAL Frequency
 
// <0=> Default (64 MHz)
// <255=> Default (16 MHz)
// <0=> 32 MHz

#ifndef CLOCK_CONFIG_XTAL_FREQ
#define CLOCK_CONFIG_XTAL_FREQ 0
// #define CLOCK_CONFIG_XTAL_FREQ 255

which was all I could find that was relevant to the XTAL change.

The firmware uploads suceesfully but doesn't run:

openocd programming logs:(chip erased before writing as this seems to effect the radio functionality on the dongle)

DONGLE:

Flash app with softdevice
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
    openocd.org/.../bugs.html
cortex_m reset_config sysresetreq
adapter speed: 1000 kHz
adapter speed: 3000 kHz
Info : No device selected, using first device.
Info : J-Link OB-SAM3U128-V2-NordicSemi compiled Jan 12 2018 16:05:20
Info : Hardware version: 1.00
Info : VTarget = 3.300 V
Info : Reduced speed from 3000 kHz to 1000 kHz (maximum).
Info : Reduced speed from 3000 kHz to 1000 kHz (maximum).
Info : clock speed 3000 kHz
Info : SWD DPIDR 0x0bb11477
Info : nRF51822.cpu: hardware has 4 breakpoints, 2 watchpoints
    TargetName         Type       Endian TapName            State       
--  ------------------ ---------- ------ ------------------ ------------
 0* nRF51822.cpu       cortex_m   little nRF51822.cpu       halted
auto erase enabled
Info : nRF51422-QFAC(build code: A1) 256kB Flash
Info : Padding image section 0 with 2112 bytes
Warn : not enough working area available(requested 32)
Warn : no working area available, falling back to slow memory writes
wrote 110592 bytes from file s130_nrf51_2.0.1_softdevice.hex in 17.862696s (6.046 KiB/s)
auto erase enabled
Warn : not enough working area available(requested 32)
Warn : no working area available, falling back to slow memory writes
wrote 79872 bytes from file Debug/kbd.bin in 12.884310s (6.054 KiB/s)
shutdown command invoked

TY eval board:

Flash app with softdevice
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
    openocd.org/.../bugs.html
cortex_m reset_config sysresetreq
adapter speed: 1000 kHz
adapter speed: 3000 kHz
Info : No device selected, using first device.
Info : J-Link Lite-Cortex-M V9 compiled Feb  2 2018 18:14:01
Info : Hardware version: 9.00
Info : VTarget = 3.324 V
Info : clock speed 3000 kHz
Info : SWD DPIDR 0x0bb11477
Info : nRF51822.cpu: hardware has 4 breakpoints, 2 watchpoints
    TargetName         Type       Endian TapName            State       
--  ------------------ ---------- ------ ------------------ ------------
 0* nRF51822.cpu       cortex_m   little nRF51822.cpu       halted
auto erase enabled
Info : nRF51422-CFAC(build code: A0) 256kB Flash
Info : Padding image section 0 with 2112 bytes
Warn : not enough working area available(requested 32)
Warn : no working area available, falling back to slow memory writes
wrote 110592 bytes from file s130_nrf51_2.0.1_softdevice.hex in 33.366196s (3.237 KiB/s)
auto erase enabled
Warn : not enough working area available(requested 32)
Warn : no working area available, falling back to slow memory writes
wrote 79872 bytes from file Debug/kbd.bin in 24.108545s (3.235 KiB/s)
shutdown command invoked

I noticed there is a difference in the device name and the "build code" but couldn't find any information on how that might effect things.

Any help would be much appreciated.

Note: that device is basically a keyboard, with a few little changes

Thanks!

[Vidar Berg]

Hi,

The 32MHz clock signal is divided by two internally on the chip. In other words, the system clock will always be 16 MHz (__SYSTEM_CLOCK).  However, for the clock source to be divided by two you need to set the non-volatile UICR.XTALFREQ register to 0x00 (see chapter 8 of the nRF51 RM). 

It's also important that you implement the workaround for PAN #78 (link).

Best regards,

Vidar

[william-krs]

Hi Vidar,

I had addeded the UICR.XTALFREQ register update to system_nrf51.c, I also added PAN #78 code to system_nrf51.c after the UICR.XTALFREQ, is this the correct implementation of PAN #78 as it doesn't state where to put it? see below:

void SystemInit(void)
{
    /* If desired, switch off the unused RAM to lower consumption by the use of RAMON register.
       It can also be done in the application main() function. */

    /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required
       to enable the use of peripherals" found at Product Anomaly document for your device found at
       https://www.nordicsemi.com/. The side effect of executing these instructions in the devices
       that do not need it is that the new peripherals in the second generation devices (LPCOMP for
       example) will not be available. */
    // added WILLY
    if (*(uint32_t *)0x10001008 == 0xFFFFFFFF)
    {     
    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
    *(uint32_t *)0x10001008 = 0xFFFFFF00;     
    NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
    while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}     
    NVIC_SystemReset();     
    while (true){}
    }
    
    NRF_CLOCK->TASKS_HFCLKSTOP = 1;
    while (NRF_CLOCK->HFCLKSTAT & (CLOCK_HFCLKSTAT_SRC_Xtal <<
    CLOCK_HFCLKSTAT_SRC_Pos));
    NVIC_SystemReset();
    
    if (is_manual_peripheral_setup_needed())
    {
        *(uint32_t volatile *)0x40000504 = 0xC007FFDF;
        *(uint32_t volatile *)0x40006C18 = 0x00008000;
    }

    /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG
       register is incorrect" found at Product Anomaly document for your device found at
       https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */
    if (is_disabled_in_debug_needed())
    {
        NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos;
    }

    /* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices,
       as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document
       for your device found at https://www.nordicsemi.com/. */
    if (is_peripheral_domain_setup_needed()){
        if (*(uint32_t volatile *)0x4006EC00 != 1){
            *(uint32_t volatile *)0x4006EC00 = 0x9375;
            while (*(uint32_t volatile *)0x4006EC00 != 1){
            }
        }
        *(uint32_t volatile *)0x4006EC14 = 0xC0;
    }
}

Also from your comments does that mean that setting the __SYSTEM_CLOCK to 32MHz was incorrect, and that CLOCK_CONFIG_XTAL_FREQ 0 was also not required?

Thanks for your help.

[Vidar Berg]

Hi, 

PAN #78 workaround should be implemented where you are calling nvic_systemreset/sd_nvic_systemreset in your code. E.g., in the app_error_handler and when your reset into DFU mode if you have implemented DFU support. 

Yes, __SYSTEM_CLOCK  must be 16, so you should revert the change you made earlier. Also, setting CLOCK_CONFIG_XTAL_FREQ  to '0' is not required since UICR.XTALFREQ changes the reset value for CLOCK.XTALFREQ to 32 Mhz.