WDT Timer Documentation Clarification

[JeanMBoones]

From page 520 of nRF52840 Product Specification 1.0 4413_417 v1.0 / 2018-03-16

If the watchdog is configured to generate an interrupt on the TIMEOUT event, the watchdog reset will be postponed with two 32.768 kHz clock cycles after the TIMEOUT event has been generated. Once the TIMEOUT event has been generated, the impending watchdog reset will always be effectuated.

From testing, I believe that this paragraph means two ticks – or about 61µS – of the 32.768kHz clock. However, the way it’s written, it’s not clear if the word “cycles” means two seconds (i.e. two complete cycles of the clock) or two ticks of the clock.

Please confirm that the timeout is 61µS, and not some other time.

[Einar Thorsrud]

Hi,

We use the normal definition of "clock cycle", which is the same as clock period: the time it takes for the clock signal to repeat it self. Or said differently: the time between for instance the rising edges of the clock signal. The clock period is 1/32768 = 30.5 μs, so you are right that two clock cycles are 61 μs.

[JeanMBoones]

Thanks for the clarification.

-J